DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/24/2024 was considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 5 and 17 are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Sato et al. JP 2001215282 A (hereinafter referred to as Sato).
Regarding Claim 5, Sato discloses a system (fig. 1, elm. 301, par. [0021]) for evaluating a semiconductor device (fig. 1, elm. 201, par. [0022]), which is for measuring an error value (par. [0023]) of a test target semiconductor device (fig. 1, elm. 201, par. [0022]) arranged on a test board (see fig. 1, semiconductor storage devices 201on a platform, par. [0022]), the system configured to: irradiate a test region (see fig. 1, par. [0022]-[0023]) in which the test target semiconductor device is arranged with a test beam (fig. 1, fast neutron beam, par. [0022]-) to measure the error value of the test target semiconductor device by the test beam (par. [0022]-[0024).
Regarding Claim 17, Sato discloses the system of claim 5, wherein a plurality of test target semiconductor devices (fig. 1, elm. 201, par. [0022]) are in the test region (see fig. 1, par. [0022]-[0023]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over Sato as applied to claim 5 above, and further in view of Hanan US 20190011495 A1.
Regarding Claim 6, Sato discloses the system of claim 5, Sato discloses to measure and count an error that occurs in the test target semiconductor device (fig. 1, elm. 201, par. [0022]-[0024]).
Sato does not disclose explicitly comprising an algorithm board.
Hanan discloses comprising an algorithm board (fig. 1, elm. 115, par. [0044]) configured to measure and count an error that occurs in the test target semiconductor device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide an Automatic Testing Equipment to communicate with the load board for testing the operation of an electronic device installed on the load board, as taught in Hanan in modifying the apparatus of Sato. The motivation would be the ATE executes pre-programmed test procedure to count the number of errors detected. (see Hanan: par. [0038]).
Regarding Claim 7, Sato and Hanan discloses the system of claim 6, Hanan discloses further comprising: a beam irradiation region (fig. 1, elm. 100, par. [0044]) in which the test board (fig. 1, elm. 150, par. [0045]) is arranged, and irradiated with the test beam (fig. 1, elm. 130, par. [0048]); and a control region (fig. 1, region of system 10 isolated from chamber 100, par. [0044]) isolated from the beam irradiation region (see fig. 1), and unirradiated with the test beam (expose only the DUT 140 to radiation and to avoid exposure of radiation to other elements such as tools and/or humans, par. [0060]).
The references are combined for the same reason already applied in the rejection of claim 6.
Regarding Claim 8, Sato and Hanan discloses the system of claim 7, Hanan discloses further comprising: a base control system (fig. 1, par. [0044], [0066], [0070]) disposed in the control region (fig. 1, region of system 10 isolated from chamber 100, par. [0044]), and configured to receive the error value of the test target semiconductor device from the algorithm board (fig. 1, elm. 115, par. [0044]); and a base analysis system configured to analyze the error value of the test target semiconductor device received from the base control system (fig. 1, par. [0044], [0066], [0070]).
The references are combined for the same reason already applied in the rejection of claim 6.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sato as applied to claim 17 above, and further in view of Paffrath et al. US 2014/0203814 A1 (hereinafter referred to as Paffrath).
Regarding Claim 18, Sato discloses the system of claim 17, wherein the test target semiconductor devices (fig. 1, elm. 201, par. [0019]).
Sato does not explicitly disclose semiconductor devices are arranged two-dimensionally in rows and columns.
Paffrath discloses semiconductor devices are arranged two-dimensionally in rows and columns (fig. 5, elm. 501, par. [0077], [0093]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide substrate with plurality of semiconductor devices used in performing soft error rate tests, as taught in Paffrath in modifying the apparatus of Sato. The motivation would be apparatus allows for performing accelerated alpha particle soft error rate measurements on a wafer level (see Paffrath: par. [0031]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COURTNEY G MCDONNOUGH whose telephone number is (571)272-6552. The examiner can normally be reached M-F 8 am-5 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, EMAN ALKAFAWI can be reached at (571) 272-4448. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/COURTNEY G MCDONNOUGH/Examiner, Art Unit 2858
/EMAN A ALKAFAWI/Supervisory Patent Examiner, Art Unit 2858 2/10/2026