Prosecution Insights
Last updated: October 01, 2026
Application No. 18/748,954

OSCILLATOR CIRCUIT, LAYOUT, AND METHOD

Non-Final OA §102
Filed
Jun 20, 2024
Priority
Apr 30, 2024 — CN 202410546608.8
Examiner
SHIN, JEFFREY M
Art Unit
Tech Center
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
842 granted / 986 resolved
+25.4% vs TC avg
Moderate +10% lift
Without
With
+9.7%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 0m
Avg Prosecution
10 currently pending
Career history
996
Total Applications
across all art units

Statute-Specific Performance

§101
1.8%
-38.2% vs TC avg
§103
48.9%
+8.9% vs TC avg
§102
26.0%
-14.0% vs TC avg
§112
10.1%
-29.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 986 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 11, and 12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (Pub 2023/0387900). As to claim 1, Lee teaches an integrated circuit (IC) comprising (Fig 5a): a voltage source (fig 2B, VDD) configured to generate a first voltage (VDD) having a temperature- dependent voltage level (paragraphs 33, and 70, the voltage and circuitry is effected by temperature changes which the oscillator does tuning to correct); and a voltage-controlled oscillator (VCO) (310) comprising a feedback path and a first VCO cell (311) configured to receive the first voltage (fig 2B, paragraph 73, receives VDD), wherein the first VCO cell comprises a series of stages (111, 121, 131, 132, 112, 123, 124, 133, 134), a first stage (111) of the series of stages is configured to output a first signal internal to the first VCO cell based on the voltage level of the first voltage and an oscillation signal propagated on the feedback path (paragraph 43 and 44) 111 is the first inverter and will receive the feedback signal), and a last stage (134) of the series of stages is configured to output a second signal external to the first VCO cell based on the first signal and the voltage level of the first voltage (paragraph 46, 134 is the last inverter in the cell and will generate the output signal). As to claim 11, Lee teaches a second VCO cell (121) coupled between the first VCO cell and the feedback path. As to claim 12, Lee teaches a frequency measurement circuit (320 and 330) coupled to the VCO and configured to generate an output signal based on a frequency of the oscillation signal (paragraphs 76 and 77). Allowable Subject Matter Claims 13-20 are allowed. Claims 2-10 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. None of the cited prior art teach or suggest the VCO cell has dummy gate with the array comprises rows as is recited in claims 2-4 and 13-20; and the voltage source in the first cell and the voltage source connected to the gate transistor in the first cell as is recited in claims 5-10. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Liu (Pub 2011/0175684) teaches a ring oscillator with temperature tuning. Tsai et al (Pub 2018/0287593) teaches a ring oscillator with a front cell receiving tuning. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEFFREY M SHIN whose telephone number is (571)270-7356. The examiner can normally be reached M-F 9am-6pm PST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at (571) 270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JEFFREY M SHIN/Primary Examiner, Art Unit 2836
Read full office action

Prosecution Timeline

Jun 20, 2024
Application Filed
Jul 30, 2026
Non-Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
95%
With Interview (+9.7%)
2y 0m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 986 resolved cases by this examiner. Grant probability derived from career allowance rate.

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