DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The indicated allowability of claims 5-6 is withdrawn in view of the newly discovered reference(s) to Zhang et al. U.S. Patent 10,103,054 cited in the record. Rejections based on the newly cited reference(s) follow.
Claim Objections
Claims 12-13, and 15 are objected to because of the following informalities:
Regarding claims 12-13, line 3, please, change “via structure;” to - - via structure. - - for proper reading.
Regarding claim 15, lines 2 and 4, the phrase of “a first metal plate….a second metal plate” is not understood because claim 15 depended on claim 10 that already defined “a first localized metal plate…a second localized metal plate” so, does applicant mean of “a first or second metal plate is the same or different from a first or second localized metal plate” Please, clarify.
For exam in claim 15, examiner assumes that the first or second metal plate is the same of the first or second localized metal plate respectively.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 5-12,14-15, and 17 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by Zhang et al. (U.S. Patent 10,103,054).
As to claim 1, Zhang discloses an apparatus as shown in figures 1-5 comprising:
a printed circuit board (PCB-308, figure 3) including sequentially stacked multi-layers (330A, 315, 330B);
a first via structure (110) that partially penetrates the multi-layers of the PCB and is connected to a first metal plate (115A) that is on a first layer of the multi-layers (30A or 330A), wherein the first metal plate (115A) is a localized conductive pattern physically isolated from a ground via (from element 250) of the PCB; and
a second via structure (120) adjacent to the first via structure (110) in a horizontal direction, partially penetrating the multi-layers of the PCB (308), and connected to a second metal plate (124A) that is on a second layer of the multi-layers, wherein the second metal plate (124A) is a localized conductive pattern physically isolated from the ground via (from element 250),
wherein a portion where the first metal plate (115A) and the second metal plate (124A) overlap each other are configured to provide a first mutual capacitive (column 4, line 34+ or 215) coupling between the first and second via structures (110, 120), figure 1C.
As to claim 2, Zhang discloses the first and second layers, see figure 1C are adjacent to each other in a vertical direction of the PCB.
As to claim 3, Zhang further comprising: a third via structure (130) adjacent to the first via structure (110) in a vertical direction, wherein a portion where the first and third via structures (110, 130) overlap in the vertical direction is configured to provide a second mutual capacitive coupling (column 5, line 14+).
As to claim 5, Zhang further comprising: a fourth via structure (240, figure 2B) adjacent to the second via structure (220) in the vertical direction,
wherein a portion where the second and fourth via structures (220, 240) overlap in the vertical direction are configured to provide a fourth mutual capacitive coupling, column 6, line 10+.
As to claim 6, Zhang discloses a fifth mutual capacitive coupling (235)
extending from the first via structure (210) toward the fourth via structure (240) is configured to be provided between the first and fourth via structures.
As to claim 7, Zhang discloses the first and second via structures (110, 120 or 210, 220) each independently include at least one of blind via hole barrel or a buried via hole barrel that partially penetrate the multi-layers.
As to claim 8, Zhang further comprising: a round via structures (figures 1A-1C) arranged around the first and second via structures (110, 120).
As to claim 9, Zhang discloses the apparatus in figure 5A includes a memory module (304, column 8, line 29+) of at least one of a compression-attached memory module (CAMM), a low power compression-attached memory module (LP-CAMM), a registered DIMM (RDIMM), and a load reduced dual in-line memory module (LRDIMM).
As to claim 10, Zhang discloses an apparatus as shown in figures 1-5 comprising:
a printed circuit board (PCB, 308) including sequentially stacked N (N is a natural number) layers (330A, 330B); and
N via structures (110, 120, 130 figure 1 or 210, 220, 230, 240, figure 2) respectively configured to transmit N signals (column 9+) and passing through each of the N layers of the PCB,
wherein a first mutual capacitive coupling (column 4, line 34+ or 215, figure 2A) is configured to be provided between first and second via structures (110, 120 or 210, 220) adjacent to each other in a horizontal direction of the PCB (308) among the N via structures by an overlap of a first localized metal plate (115A) extending from the first via structure (110 or 210) and a second localized metal plate (124A) extending from the second via structure (120, 220), wherein the first and second localized metal plates (115A, 124A) are localized conductive patterns physically isolated from a ground via (250) of the PCB, and
a second mutual capacitive coupling (215) is configured to be provided between third and fourth via structures (230, 240) overlapping each of the first and second via structures (210, 220) in a vertical direction among the N via structures.
As to claim 11, Zhang discloses a third mutual capacitive coupling (225) extending from the first via structure (210) toward the third via structure (230) is configured to be provided between the first and third via structures (210, 230).
As to claim 12, Zhang discloses a third mutual capacitive coupling (235) extending from the first via structure (210) toward the fourth via structure (240) is configured to be provided between the first and fourth via structures.
As to claim 14, Zhang discloses a third mutual capacitive coupling (225) extending from the second via structure (220) toward the fourth via structure (240) is configured to be provided between the second and fourth via structures (220, 240).
As best understood to claim 15, Zhang further comprising:
[[a]] the first localized metal plate (115A) connected to the first via structure (110) in a layer on which the first via structure (110, 210) is arranged from among the N layers; and
[[a]] the second localized metal plate (124A) connected to the third via structure (130 or 230) in a layer on which the third via structure is arranged from the N layers,
wherein a portion where the first and second metal plates (115A, 124A) overlap each other is configured to provide a third mutual capacitive coupling (225, figure 2B) between the first and third via structures.
As to claim 17, Zhang discloses the apparatus is a memory module
(304, column 8, line 29+) included in any one of a compression-attached memory module (CAMM), a low power compression-attached memory module (LP-CAMM), a registered DIMM (RDIMM), and a load reduced dual in-line memory module (LRDIMM).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over
Zhang et al. (U.S. Patent 10,103,354) in view of Mizutani et al. (U.S. 2014/0311772)
As to claim 18, Zhang discloses a via structure (110, 120, or 130, figures 1A-1C) as shown in figures 1-4 comprising:
a barrel (stacked 110) on a printed circuit board (PCB-308, figure 3A) that includes sequentially stacked multi-layers (column 4, line 3, 330A, 315, 330B); and a conductive material film (110B),
wherein the barrel (stack 110) is configured to provide a signal entry point (top
entry pad 110A) and a signal exit point (bottom exit pad 110A, see figure 1C) by partially penetrating the multi-layers (308), and a layer on which a localized metal plate (111A, 113A, or 115A) that is physically isolated from a ground via (column 5, line 61+, element 250) on the PCB (308) is arranged from among the penetrated layers between the signal entry point and the signal exit point is configured to provide a mutual capacitance point, and
the conductive material film (110B) in a region of the signal entry and exit points is arranged to be greater in size than the conductive material film in a region of the mutual capacitance point, see column 7, line 41 to column 8, line 3, figure 2A.
Zhang does not specifically disclose an insulating material film embedded in a center of the barrel.
Mizutani teaches a printed wiring board as shown in figure 1 comprising an
insulating material film (33a) embedded in a center of the barrel, para-0039+.
It would have been obvious to one having ordinary skill in the art before the
effective filling date to have a teaching of Mizutani employed in the apparatus of
Zhang in order to provide excellent isolation characteristic for the plating hole
or barrel.
Regarding claim 19, Zhang as modified by Mizutani discloses the barrel (110) includes at least one of a blind via hole barrel or a buried via hole barrel.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over
Zhang in view of Mizutani, and further in view of Takeda (U.S. 2011/0226516).
Regarding claim 20, Zhang as modified by Mizutani discloses all of the
limitations of claimed invention except for the barrel includes a laser via hole barrel.
Takeda teaches a wiring board (1) as shown in figure 1 comprising the barrel (the
PTH 40) includes a laser via hole barrel, para-0059.
It would have been obvious to one having ordinary skill in the art before the
effective filling date to have a teaching of Takeda employed in the apparatus of Zhang and Mizutani in order to provide a micro-via structure, reduce parasitic capacitance, and enhanced signal integrity characteristic.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over
Zhang in view of Takeda (U.S. 2011/0226516).
Regarding claim 16, Zhang discloses all of the limitations of claimed invention except for the N via structures each include a laser via hole (LVH) barrel passing through each of the N layers.
Takeda teaches a wiring board (1) as shown in figure 1 comprising the N via structures each include a laser via hole (LVH, para-0059+) barrel passing through each of the N layers.
It would have been obvious to one having ordinary skill in the art before the
effective filling date to have a teaching of Takeda employed in the apparatus of Zhang in order to provide a micro-via structure, reduce parasitic capacitance, and enhanced signal integrity characteristic.
Allowable Subject Matter
Claims 4 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN T DINH whose telephone number is (571)272-1929. The examiner can normally be reached 8am-5pm, M-F.
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/TUAN T DINH/Primary Examiner, Art Unit 2847
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