DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Priority
The present application, 18/749198, claims priority to Provisional Application 63/524289, filed on June 30, 2023. The claim for priority through this chain is acknowledged as properly supported under 35 U.S.C. § 119(e).
Information Disclosure Statement
The Information Disclosure Statement (IDS) submitted on June 20, 2024 has been considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 7 rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Regarding Claim 7, it states, “the first erase block includes a second offset factor corresponding thereto in association with sensing operations…“ This claim does not further limit the claim from which it depends, Claim 5, which identifies, “a first offset factor corresponding to the first erase block and a second offset factor corresponding to the second erase block.” As written, the second offset factor would need to correspond with both the first and second erase block, without appropriate support given for such a correspondence. In the interest of compact prosecution, this limitation will be read as, “the first erase block includes a first offset factor corresponding thereto in association with sensing operations…”
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-7 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2014/0136765 A1 to Eun Chu Oh, et al. (hereafter Oh) in view of US 7,196,928 B2 to Jian Chen (hereafter Chen) and US 2011/0194350 A2 to Tommaso Vali, et al. (hereafter Vali).
Regarding Independent Claim 1, Oh discloses an apparatus, comprising:
a memory array (A 3D memory array: Oh, ¶[0046]) comprising a plurality of strings of memory cells (Strings of memory cells: Oh, ¶[0046]), wherein each string of the plurality of strings comprises:
a first group of memory cells (A first sub-block: Oh, Figure 1)
coupled to a first group of access lines (Coupled to the same word lines: Oh, ¶[0048]) and
corresponding to a first erase block (Erase operations taking place at the sub-block level: Oh, ¶[0046]); and
a second group of memory cells (A second sub-block: Oh, Figure 1)
coupled to a second group of access lines (Coupled to the same word lines: Oh, ¶[0048]) and
corresponding to a second erase block (Erase operations taking place at the sub-block level: Oh, ¶[0046]); and
control circuitry coupled to the memory array (A controller coupled to the memory array: Oh, ¶[0044]) and configured to:
receive a command corresponding to a sensing operation (Receiving a read command: Oh, ¶[0044])
to be performed on a selected access line (Reading data from a specific sub-block: Oh, ¶[0052])
of the first group of access lines (Reading data from a specific sub-block: Oh, ¶[0052]); and
determine an adjusted sense voltage (Applying a voltage bias: Oh, ¶[0052])
to be applied to the selected access line (Applying the bias to the selected memory cells: Oh, ¶[0052])
in association with performing the sensing operation (During the read operation: Oh, ¶[0052]),
wherein the adjusted sense voltage is based on:
a quantity of the second group of access lines that are programmed (Setting the read bias based on the program/erase states of adjacent sub-blocks: Oh, ¶[0093]).
When a claim covers several structures or compositions, either generically or as alternatives, the claim is deemed anticipated if any of the structures or compositions within the scope of the claim is known in the prior art. (See. Brown v. 3M, 265 F.3d 1349, 1351, 60 USPQ2d 1375, 1376 (Fed. Cir. 2001)). When the species is clearly named, the species claim is anticipated no matter how many other species are additionally named (See MPEP § 2131.02.II). Therefore, Claim 1 would be properly rejected under 35 U.S.C. 102 as entirely anticipated by Oh. In the interest of compact prosecution, however, the remaining species will be treated separately here.
Chen teaches adjusting a sense voltage based on the programming status of adjacent wordlines (Adjusting based on programming state of adjacent wordlines: Chen, col.26:24-27). Chen teaches this method helps compensate for localized back pattern effects during reading operations (Chen, col.26:22-24). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the local word line analysis of Chen with the sub-block biasing method of Oh, with a reasonable expectation of success. Both inventions are well known in the field of back pattern effect compensation during read operations and the combination of known inventions with predictable results is obvious and not patentable.
Further, Vali teaches modifying the sense voltage during a reading operation based on a totality of the status of the entire bitline, regardless of partitioning into sub-blocks (Adjusting bias based on a totality of conditions throughout the bitline: Vali, ¶[0029]). Vali teaches this method can be used to compensate for back pattern effect in a memory device (Vali, ¶[0029]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the whole line analysis of Vali with the sub-block biasing method of Oh, with a reasonable expectation of success. Both inventions are well known in the field of back pattern effect compensation during read operations and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 2, Oh discloses the apparatus of claim 1, wherein the sensing operation
is a read operation or a program verify operation (The sensing operation is a read operation: Oh, ¶[0052]).
Regarding Claim 3, Oh discloses the apparatus of claim 1, wherein the adjusted sense voltage
is an offset from a default sense voltage (Referring to adjusting a read bias, suggesting offsetting an initial value by some amount: Oh, ¶[0047])
corresponding to the sensing operation (The read bias being used in a read operation: Oh, ¶[0047]), and
wherein the offset is determined based on a quantization factor corresponding to:
the quantity of the first group of access lines that are programmed (Adjusting based on programming state of adjacent wordlines: Chen, col.26:24-27); or
the quantity of the second group of access lines that are programmed (Setting the read bias based on the program/erase states of adjacent sub-blocks: Oh, ¶[0093]); or
both (Adjusting bias based on a totality of conditions throughout the bitline: Vali, ¶[0029]).
Regarding Claim 4, Oh discloses the apparatus of claim 1, further comprising
an external system controller (Memory controller 110: Oh, ¶[0047) configured to:
track erase block program state information corresponding to the plurality of erase blocks (Tracking the sub-block programming state: Oh, Figure 12);
determine the quantization factor based on the tracked erase block program state information (Adjusting read bias based on the program/erase status of the associated sub-blocks: Oh, ¶[0126]); and
provide the quantization factor to the control circuitry with the command corresponding to the sensing operation (Adjusting the read voltage by an identified read bias depending on the program/erase status of associated sub-blocks: Oh, ¶[0052]); and
wherein the quantization factor corresponds to:
a portion of a total quantity of access lines of the first erase block that are in a programmed state (Adjusting based on programming state of adjacent wordlines: Chen, col.26:24-27); or
a portion of a total quantity of access lines of the second erase block (Setting the read bias based on the program/erase states of adjacent sub-blocks: Oh, ¶[0093]); or
both (Adjusting bias based on a totality of conditions throughout the bitline: Vali, ¶[0029]).
Regarding Claim 5, Oh discloses the apparatus of claim 1, wherein the adjusted voltage
is further determined based on
a first offset factor corresponding to the first erase block (Adjusting the read bias due to various factors, such as erase count: Oh, ¶[0146]; or physical position: Oh, ¶[0126]) and
a second offset factor corresponding to the second erase block (Adjusting the read bias due to various factors, such as erase count: Oh, ¶[0146]; or physical position: Oh, ¶[0126]).
Regarding Claim 6, Oh discloses the apparatus of claim 5, wherein
the first offset factor and the second offset factor are the same (Additional adjustments are inherently optional and may be omitted for all sub-blocks).
Regarding Claim 7, Oh discloses the apparatus of claim 5, wherein
the first erase block includes
a first offset factor (Adjusting the read bias due to various factors, such as erase count: Oh, ¶[0146]; or physical position: Oh, ¶[0126])
corresponding thereto in association with sensing operations (Adjusting the read bias in response to the program/erase count: Oh,¶[0127])
performed on selected access lines of the second erase block, and wherein
the second erase block includes
a second offset factor (Adjusting the read bias due to various factors, such as erase count: Oh, ¶[0146]; or physical position: Oh, ¶[0126])
corresponding thereto in association with sensing operations (Adjusting the read bias in response to the program/erase count: Oh,¶[0127])
performed on selected access lines of the second erase block (The program/erase data for all associated sub-blocks taken into account during a read request: Oh, ¶[0130]).
Regarding Claim 19, Oh discloses the apparatus of claim 12, but fails to disclose the further limitations of Claim 19. Vali, however, discloses an apparatus as in Claim 12, wherein the erase block program state information comprises
three or fewer bits (The compensation voltage consisting of a limited number of bits: Vali, ¶[0036]; Note: In this example, Vali expresses this value as four bits ranging from ‘0000’ to ‘0111’. The MSB in this example does not change, limiting the functional data to only three bits.).
Vali teaches this limitation allows the back pattern offset to be stored in a limited number of latches (Vali, ¶[0030]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the limited bitline data of Vali with the sub-block biasing method of Oh, with a reasonable expectation of success. Both inventions are well known in the field of back pattern effect compensation during read operations and the combination of known inventions with predictable results is obvious and not patentable.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2014/0136765 A1 to Eun Chu Oh, et al. (hereafter Oh), US 7,196,928 B2 to Jian Chen (hereafter Chen) and US 2011/0194350 A2 to Tommaso Vali, et al. (hereafter Vali), in view of US 2018/0012667 A1 to Xiying Costa (hereafter Costa).
Regarding Claim 8, Oh discloses the apparatus of claim 1, including appropriate pass voltages (Oh, ¶[0161]), but fails to disclose applying different pass voltages to word lines based on programming state. Costa, however, discloses an apparatus as in Claim 1, wherein:
the control circuitry (Control circuitry 110: Costa, Figure 3) is configured to, in association with performing the sensing operation on the selected access line of the first erase block:
apply a read pass voltage to programmed access lines of the second erase block (Applying a high read pass voltage to programmed memory lines: Costa, ¶[0107]); and
apply a reduced read pass voltage to erased access lines of the second erase block in order to emulate programmed access line (Applying a reduced pass voltage to erased memory lines: Costa, ¶[0108]).
Costa teaches adjusting the applied pass voltage can help avoid disturbances to programmed memory cells (Costa, ¶[0104]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the variable pass voltage of Costa with the sub-block biasing method of Oh, with a reasonable expectation of success. Both inventions are well known in the field of back pattern effect compensation during read operations and the combination of known inventions with predictable results is obvious and not patentable.
Claim(s) 9-16, 18, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2014/0136765 A1 to Eun Chu Oh, et al. (hereafter Oh) in view of US 7,196,928 B2 to Jian Chen (hereafter Chen).
Regarding Independent Claim 9, Oh discloses a method, comprising:
tracking,
via a controller (Controller 110: Oh, Figure 1)
external to a memory device (A 3D memory array: Oh, ¶[0046]) comprising a plurality of erase blocks (The array consisting of a series of sub-blocks: Oh, Figure 1),
respective erase block program state statuses for the plurality of erase blocks (Tracking the erase block statuses for the plurality of erase blocks: Oh, Figure 12);
providing, to the memory device:
a command corresponding to a sensing operation (Receiving a read command: Oh, ¶[0044])
to be performed
on a selected access line (Reading data from a specific sub-block: Oh, ¶[0052]) of a first group of access lines
corresponding to a first erase block (Reading data from a specific sub-block: Oh, ¶[0052]); and
determining, via the memory device,
an offset (Applying a voltage bias: Oh, ¶[0052]) by which a sense voltage to be applied to the selected access line is to be adjusted (Applying the bias to the selected memory cells: Oh, ¶[0052])
in association with performing the sensing operation (During the read operation: Oh, ¶[0052]).
Oh is primarily focused on adjusting the read bias voltage based on the program/erase state of sub-blocks other than the selected sub-block for reading. Chen, however, discloses adjusting a sense voltage based on the local programming status of adjacent wordlines, that is, within the first erase block (Adjusting based on programming state of adjacent wordlines: Chen, col.26:24-27). Chen teaches this method helps compensate for localized back pattern effects during reading operations (Chen, col.26:22-24). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the local word line analysis of Chen with the sub-block biasing method of Oh, with a reasonable expectation of success. Both inventions are well known in the field of back pattern effect compensation during read operations and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 10, Oh discloses the method of claim 9, wherein the memory device comprises
a second erase block (A second sub-block: Oh, Figure 1)
including a second group of access lines (Coupled to the same word lines: Oh, ¶[0048]), wherein
the first group of access lines and the second group of access lines correspond to a memory array comprising a plurality of strings of memory cells (The first and second groups of word lines comprising a plurality of strings of memory cells: Oh, Figure 3), wherein
a first string of the plurality of strings comprises:
a first group of memory cells coupled to the first group of access lines and corresponding to the first erase block (The first group of word lines comprising a plurality of strings of memory cells: Oh, Figure 3); and
a second group of memory cells coupled to the second group of access lines and corresponding to the second erase block (The second group of word lines comprising a plurality of strings of memory cells: Oh, Figure 3); and wherein
the method further comprises:
determining, via the memory device,
the offset by which the sense voltage to be applied to the selected access line (Referring to adjusting a read bias, suggesting offsetting an initial value by some amount: Oh, ¶[0047])
is to be adjusted in association with performing the sensing operation (Adjusting read bias based on the program/erase status of the associated sub-blocks: Oh, ¶[0126])
based on erase block program state information corresponding to the second erase block (Adjusting the read voltage by an identified read bias depending on the program/erase status of associated sub-blocks: Oh, ¶[0052]).
Regarding Claim 11, Oh discloses the method of claim 10, wherein the memory device comprises
a third erase block (A second sub-block: Oh, Figure 1)
including a third group of access lines corresponding to the memory array (The first and third groups of word lines comprising a plurality of strings of memory cells: Oh, Figure 3),
wherein the first string further comprises:
a first group of memory cells coupled to the first group of access lines and corresponding to the first erase block (The first group of word lines comprising a plurality of strings of memory cells: Oh, Figure 3); and
a third group of memory cells coupled to the third group of access lines and corresponding to the third erase block (The third group of word lines comprising a plurality of strings of memory cells: Oh, Figure 3); and wherein
the method further comprises:
determining, via the memory device,
the offset by which the sense voltage to be applied to the selected access line (Referring to adjusting a read bias, suggesting offsetting an initial value by some amount: Oh, ¶[0047])
is to be adjusted in association with performing the sensing operation (Adjusting read bias based on the program/erase status of the associated sub-blocks: Oh, ¶[0126])
based on erase block program state information corresponding to the third erase block (Adjusting the read voltage by an identified read bias depending on the program/erase status of associated sub-blocks: Oh, ¶[0052]).
Regarding Independent Claim 12, Oh discloses an apparatus, comprising:
a memory device (A 3D memory array: Oh, ¶[0046]) comprising
a memory array comprising a plurality of erase blocks (The array consisting of a series of sub-blocks: Oh, Figure 1); and
a controller external to the memory device (Controller 110: Oh, Figure 1) and configured to:
track respective erase block program state statuses for the plurality of erase blocks (Tracking the erase block statuses for the plurality of erase blocks: Oh, Figure 12);
provide, to the memory device:
a command corresponding to a sensing operation (Receiving a read command: Oh, ¶[0044]) to be performed on a selected access line (Reading data from a specific sub-block: Oh, ¶[0052]) of a first group of access lines corresponding to a first erase block (Reading data from a specific sub-block: Oh, ¶[0052]); and
wherein the memory device is configured to determine
an offset (Applying a voltage bias: Oh, ¶[0052]) by which a sense voltage to be applied to the selected access line (Applying the bias to the selected memory cells: Oh, ¶[0052])
is to be adjusted in association with performing the sensing operation (During the read operation: Oh, ¶[0052]).
Oh is primarily focused on adjusting the read bias voltage based on the program/erase state of sub-blocks other than the selected sub-block for reading. Chen, however, discloses adjusting a sense voltage based on the local programming status of adjacent wordlines, that is, within the first erase block (Adjusting based on programming state of adjacent wordlines: Chen, col.26:24-27). Chen teaches this method helps compensate for localized back pattern effects during reading operations (Chen, col.26:22-24). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the local word line analysis of Chen with the sub-block biasing method of Oh, with a reasonable expectation of success. Both inventions are well known in the field of back pattern effect compensation during read operations and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 13, Oh discloses the apparatus of claim 12, wherein
the command comprises the erase block program state information corresponding to the first erase block (In response to receiving a read command from the host, Controller 110 determines the proper read bias voltage taking into account the sub-block program/erase status: Oh, ¶¶[0132-0133]).
Regarding Claim 14, Oh discloses the apparatus of claim 12, wherein
the erase block program state information corresponding to the first erase block indicates a portion of the first group of access lines that are programmed (The operation being performed in accordance with Claim 12 is a sensing operation. Therefore, at a minimum, the command to read from the sub-block must include information on which lines have been programmed).
Regarding Claim 15, Oh discloses the apparatus of claim 12, wherein
the memory device comprises a memory array comprising a plurality of strings of memory cells (A memory array comprising a plurality of memory cells: Oh, Figure 3),
wherein a first string of the plurality of strings comprises:
a first group of memory cells coupled to the first group of access lines corresponding to the first erase block (The first group of word lines comprising a plurality of strings of memory cells: Oh, Figure 3); and
a second group of memory cells coupled to a second group of access lines corresponding to a second erase block (The second group of word lines comprising a plurality of strings of memory cells: Oh, Figure 3).
Regarding Claim 16, Oh and Chen disclose the apparatus of claim 15, wherein
a controller (Controller 110: Oh, Figure 1) external to the memory device (A 3D memory array: Oh, ¶[0046]) is configured to provide, to the memory device,
erase block program state information corresponding to the second erase block (Tracking the erase block statuses for the plurality of erase blocks: Oh, Figure 12); and
wherein the memory device is configured to
determine the offset (Applying a voltage bias: Oh, ¶[0052]) by which the sense voltage to be applied to the selected access line is to be adjusted (Applying the bias to the selected memory cells: Oh, ¶[0052])
in association with performing the sensing operation based (During the read operation: Oh, ¶[0052])
on the provided erase block program state information corresponding to the first erase block (Adjusting based on programming state of adjacent wordlines: Chen, col.26:24-27) and
on the provided erase block program state information corresponding to the second erase block (Setting the read bias based on the program/erase states of adjacent sub-blocks: Oh, ¶[0093]).
Regarding Claim 18, Oh discloses the apparatus of claim 16, wherein the memory device is configured to,
in response to receiving a particular command from the controller:
generate current erase block program state information corresponding to one or more of the plurality of erase blocks (Tracking program/erase state information: Oh, Figure 12); and
provide the current erase block program state information to the controller (Updating program/erase data to the controller: Oh, ¶[0126]).
Regarding Claim 20, Oh discloses the apparatus of claim 12, wherein the apparatus comprises
a memory sub-system (The memory system being one of a plurality of memory systems: Oh, ¶[0175]), wherein the controller comprises a sub-system controller (Controller 110 being connected to SSD controller 1210: Oh, ¶[0175]), and wherein the memory device is a NAND flash memory device (The memory device being a NAND flash memory device: Oh, ¶[0175]).
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2014/0136765 A1 to Eun Chu Oh, et al. (hereafter Oh) and US 7,196,928 B2 to Jian Chen (hereafter Chen) in view of US 11,145,356 B2 to Fu-Cheng Tsai, et al. (hereafter Tsai).
Regarding Claim 17, Oh discloses the apparatus of claim 16, wherein
the erase block program state information corresponding to the first erase block and provided to the memory device (Tracking the erase block statuses for the plurality of erase blocks: Oh, Figure 12).
Oh does not, however, discloses where the quantization factor is indicative of a quantity of the first group of access lines that are programmed. Tsai, however, discloses an apparatus as in Claim 16, wherein the quantization factor is indicative of a quantity of the first group of access lines that are programmed (Calculating the enabled number of wordlines in a memory cell array: Tsai, col.3:63-67).
Tsai teaches capturing an analog conversion of the enabled word lines allows the array to use a relatively small value, improving efficiency (Tsai, col.3:30-37). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the analog capture value as in Tsai with the sub-block read bias of Oh, with a reasonable expectation of success. Both inventions are well known in the field of back pattern effect compensation and the combination of known inventions with predictable results is obvious and not patentable.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
NPL: Wei-Chen Chen et al., "Study of the programming sequence induced back-pattern effect in split-page 3D vertical-gate (VG) NAND flash," Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), Hsinchu, Taiwan, 2014, pp. 1-2.
US 2020/0243147 A1 to Xiang Yang: Teaching adjusting programming voltage based on program/erase status of adjacent wordlines.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER LANE REECE whose telephone number is (571)272-0288. The examiner can normally be reached Monday - Friday 7:30am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CHRISTOPHER LANE REECE/Examiner, Art Unit 2824 /HAN YANG/Primary Examiner, Art Unit 2824