DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after allowance or after an Office action under Ex Parte Quayle, 25 USPQ 74, 453 O.G. 213 (Comm'r Pat. 1935). Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, prosecution in this application has been reopened pursuant to 37 CFR 1.114. Applicant's submission filed on December 2, 2025 has been entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 2 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Willard et al. (WO 2019/191140 A2 cited in the Information Disclosure Statement filed December 2, 2025, hereafter Willard).
Claim 2: Willard teaches a FET switch stack (Figure 4) comprising:
a plurality of field effect transistors (FETs) connected in series (M1-Mn); and
a first drain-source resistor network (Rds) including a serial connection of at least two first drain-source resistors (Rds connected between M0 and M1, and Rds connected between M1 and M2) connected to each other at a first tapping point (Vdrain), the serial connection of the at least two first drain-source resistors having a first terminal (connected between M1 and M2) and a second terminal (connected between M1 and M2);
wherein:
the plurality of FETs is connected at one end to a first radio frequency (RF) terminal;
the plurality of FETs comprises a first FET (M1) and a second FET (M2), a source terminal of the first FET being connected to a drain terminal of the second FET ([0057]);
the first terminal (connected between M1 and M2) is coupled to a drain terminal of the first FET and the second terminal is coupled to a source terminal of the first FET (connected between M1 and M0), and
the FET switch stack is configured such that, during operation with an applied RF signal, the first tapping point and a gate terminal of the first FET are electrically at different RF voltage potentials (Figures 5A-5C that show the operation of the FET stack, where Vgate and Vdrain are at different potentials for the ON and OFF state).
Allowable Subject Matter
Claim 3 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 3, the prior art does not fairly teach or suggest a second drain-source resistor network including a serial connection of at least two second drain-source resistors connected to each other at a second tapping point in combination with the limitations of claim 3.
Willard teaches a second drain-source resistor network (Rds connected between M1 and M2, and Rds connected between M2 and Mn). Willard does not specifically teach a second tapping point.
Claims 4-21 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 4, the prior art does not fairly teach or suggest the limitations of claim 4 for the reasons stated in the Non-Final Rejection dated March 27, 2025.
Claims 5-21 are allowed merely for being dependent on claim 4.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLLEEN J O'TOOLE whose telephone number is (571)270-1273. The examiner can normally be reached Monday - Friday, 9:00 am - 6:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at (571)270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C.J.O/Examiner, Art Unit 2849
/Menatoallah Youssef/SPE, Art Unit 2849