DETAILED ACTION
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election without traverse of claims 1-12 and 15-20 in the reply filed on 03/17/2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6, 9, 10, 15, 16, and 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Grobis, US 20200006432 A1.
As to claim 1, Grobis discloses an apparatus (see Fig 1A) comprising:
a cross-bar memory array (see Fig 2A and Para [0040]) comprising a plurality of first conductive lines (see Fig 2A Refs WL_10 and WL20), a plurality of second conductive lines (see Fig 2A Refs LBL_11 and LBL_12), a plurality of programmable resistance memory cells (see Fig 2C3 Ref M_233 and Fig 6A Refs 230 and 228d), and a plurality of capacitors (see Fig 6A Ref Cr), each capacitor associated with a memory cell (see Fig 6A Ref 226d), each programmable resistance memory cell between one of the first conductive lines and one of the second conductive lines (see Fig 2A);
each programmable resistance memory cell comprising: a two terminal threshold switching selector (see Fig 7A Ref 702); a conductive region (see Fig 7A Ref 710b) in contact with the two terminal threshold switching selector; and a programmable resistance memory element (see Fig 7A Ref 704) in series with the two terminal threshold switching selector (see Fig 7A Refs 702 and 704);
the capacitor associated with a particular memory cell (see Fig 6A Ref 226d and Fig 7A leftmost stack) comprises a first electrode (see Fig 7A Ref 710b) formed by the conductive region of the particular memory cell, a dielectric adjacent (see Fig 7A Ref 712 and Para [0146]) to the first electrode, and a second electrode adjacent (see Fig 7A Ref 714) to the dielectric.
As to claim 2, Grobis discloses the apparatus of claim 1, further comprising
a control circuit (see Fig 1B) configured to drive a read current (see Grobis Para [0084]) to a selected first conductive line (see Grobis Para [0084]) while providing a select voltage to a selected second conductive line (see Grobis Para [0084]), wherein
the capacitor associated with the particular memory cell is configured to absorb a snapback current (see Grobis Para [0139]) due to switching on of the two terminal threshold switching selector of the particular memory cell (see Grobis Para [0099]).
As to claim 3, Grobis discloses the apparatus of claim 1, wherein
the capacitor associated with the particular memory cell is connected in parallel with the programmable resistance memory element (see Fig 6A).
As to claim 4, Grobis discloses the apparatus of claim 1, wherein:
the dielectric of the capacitor associated with the particular memory cell surrounds the conductive region of the particular memory cell (see Fig 7A Refs 712, 714, and 7B, and Fig 7B); and the second electrode of the capacitor associated with the particular memory cell surrounds dielectric of the capacitor, the dielectric between the first electrode and the second electrode (see Fig 7B Ref 714).
As to claim 5, Grobis discloses the apparatus of claim 4, wherein
the programmable resistance memory element comprises a magnetic tunnel junction (MTJ) having a reference layer, a tunnel barrier, and a free layer (see Grobis Para [0039] and Fig 5D Ref 506; Examiner takes notice the claimed layers are common and well known for magnetic tunneling junction structures.).
As to claim 6, Grobis discloses the apparatus of claim 5, wherein:
the dielectric of the capacitor associated with the particular memory cell extends to surround the tunnel barrier of the MTJ of the particular memory cell (see Fig 7A Refs 712, 714, 704, and 7B, and Fig 7B); and the second electrode of the capacitor associated with the particular memory cell extends to surround the tunnel barrier of the MTJ of the particular memory cell, the extended portion of the dielectric residing between the tunnel barrier of the MTJ and the extended portion of the second electrode (see Fig 7A Ref 704 and Fig 7B Ref 714).
As to claim 9, Grobis discloses the apparatus of claim 1, wherein
the two terminal threshold switching selector comprises an Ovonic Threshold Switch (OTS) (see Grobis Para [0096]).
As to claim 10, Grobis discloses the apparatus of claim 9, wherein
the programmable resistance memory element comprises a magnetic tunnel junction (MTJ) having a reference layer, a tunnel barrier, and a free layer (see Grobis Para [0039] and Fig 5D Ref 506), the capacitor associated with the particular memory cell is connected in parallel with the MTJ to provide a low impedance path in parallel with the tunnel barrier (see Fig 6A; The functional language is inherent to the disclosed structure.).
As to claim 15, Grobis discloses a memory system (see Fig 1A) comprising:
a cross-bar memory array (see Fig 2A and Para [0040]) comprising a plurality of first conductive lines (see Fig 2A Refs WL_10 and WL20), a plurality of second conductive lines (see Fig 2A Refs LBL_11 and LBL_12), and a plurality of programmable resistance memory cells (see Fig 2C3 Ref M_233 and Fig 6A Refs 230 and 228d), each programmable resistance memory cell between one of the first conductive lines and one of the second conductive lines (see Fig 2C3 Ref M_233),
each programmable resistance memory cell comprising: an Ovonic Threshold Switch (OTS) (see Fig 7A Ref 702 and Para [0096]) having a first surface and a second surface (see Fig 7A Ref 702); a first conductive region (see Fig 7A Ref 710a) in contact with the first surface of the OTS; a second conductive region (see Fig 7A Ref 710b) in contact with the second surface of the OTS; a magnetic tunnel junction (MTJ) (see Grobis Para [0039] and Fig 5D Ref 506) in series with the OTS (see Fig 7A Refs 702 and 704), the MTJ having a reference layer, a tunnel barrier, and a free layer (see Grobis Para [0039] and Fig 5D Ref 506; Examiner takes notice the claimed layers are common and well known for magnetic tunneling junction structures.); and
a capacitor (see Fig 6A Ref Cr) in parallel with the MTJ (see Fig 6A Refs Cr and 230), the capacitor comprising a first electrode (see Fig 7A Ref 710b), a second electrode (see Fig 7A Ref 714), and a dielectric between the first electrode and the second electrode (see Fig 7A Ref 712 and Para [0146), wherein
the first electrode is formed by the second conductive region (see Fig 7A Ref 710b), the dielectric surrounds the second conductive region (see Fig 7A Refs 712, 714, 704, and 7B, and Fig 7B), the second electrode surrounds the dielectric (see Fig 7A Ref 704 and Fig 7B Ref 714).
As to claim 16, Grobis discloses the memory system of claim 15, wherein
the second electrode of the capacitor of a particular memory cell is electrically connected to a first conductive line connected to the particular memory cell (see Grobis Fig 6A Refs Cr, S1, and B).
As to claim 18, Grobis discloses the memory system of claim 15.
Claim 18 recites substantially the same limitations as claim 6.
All the limitations of claim 18 have already been disclosed by Grobis in claim 6 above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 11, 12, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Grobis, US 20200006432 A1, in view of Hansen, US 20190165263 A1.
As to claim 11, Grobis discloses the apparatus of claim 1, wherein
the dielectric of the capacitor comprises a dielectric material.
Grobis does not appear to explicitly disclose a high-k dielectric material (see Hansen Fig 1 Ref 108 and Para [0034]).
Hansen discloses a high-k dielectric material.
It would have been obvious to one skilled in the art at the time of the effective filing of the invention that an apparatus, as disclose by Grobis, may incorporate a particular encapsulation layer, as disclose by Hansen. The inventions are well known variants of memory structure implementing OTS selectors, and the combination of known inventions which produces predictable results is obvious and not patentable. Further evidence to the obviousness of their combination is Hansen’s attempt to protect structures from oxidizing environments (see Hansen Para [0034]).
As to claim 12, Grobis discloses the apparatus of claim 1, wherein
the dielectric of the capacitor comprises tantalum pentoxide (see Hansen Fig 1 Ref 108 and Para [0038]).
As to claim 19, Grobis discloses the memory system of claim 15.
Claim 19 recites substantially the same limitations as claim 11.
All the limitations of claim 19 have already been disclosed by Grobis and Hansen in claim 11 above.
Claim(s) 17 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Grobis, US 20200006432 A1, in view of Ambrosi, US 20250221317 A1.
As to claim 17, Grobis discloses the memory system of claim 15, wherein
the second electrode of the capacitor of a particular memory cell (see Grobis Fig 6A Ref 226d and Fig 7A leftmost stack) is electrically connected to one of layers of the MTJ of the particular memory cell (see Grobis Fig 6A; Both electrodes of the capacitor are electrically connected to the layers of the MTJ.).
Grobis does not appear to explicitly disclose the reference layer of the MTJ of the particular memory cell and the free layer of the MTJ of the particular memory cell.
Ambrosi discloses the reference layer of the MTJ of the particular memory cell and the free layer of the MTJ of the particular memory cell (see Ambrosi Para [0021] and Fig 1A).
It would have been obvious to one skilled in the art at the time of the effective filing of the invention that a memory structure, as disclose by Grobis, may incorporate a particular MTJ layer, as disclose by Ambrosi. The inventions are well known variants of memory structure implementing OTS selectors, and the combination of known inventions which produces predictable results is obvious and not patentable. Further evidence to the obviousness of their combination is Ambrosi’s attempt to improve memory densities (see Ambrosi Para [0019]).
As to claim 20, Grobis and Ambrosi discloses the memory system of claim 17.
Claim 20 recites substantially the same limitations as claim 2.
All the limitations of claim 20 have already been disclosed by Grobis in claim 2 above.
Allowable Subject Matter
Claim(s) 7 and 8 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art does not appear to disclose (as recited in claim 7):
the second electrode is in direct electrical contact with one of the reference layer of the MTJ and the free layer of the MTJ.
The prior art does not appear to disclose (as recited in claim 8):
the second electrode is in direct electrical contact with the first conductive line to which the particular memory cell is connected.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Mantagazza, US 20160254052 A1 discloses a plurality of capacitors.
Inuzuka, US 20190295640 A1 discloses absorbing a snapback current.
Chang, US 20240389486 A1 discloses a plurality of capacitors.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEROME LARRY LEBOEUF whose telephone number is (571)272-7612. The examiner can normally be reached M-Th: 8:00AM - 6:00PM EST.
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/JEROME LEBOEUF/Primary Examiner, Art Unit 2824 - 05/27/2026
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