DETAILED ACTION
Examiner’s Note
The examiner has cited particular passages including column and line numbers, paragraphs as designated numerically and/or figures as designated numerically in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claims, other passages, paragraphs and figures of any and all cited prior art references may apply as well. It is respectfully requested from the applicant, in preparing an eventual response, to fully consider the context of the passages, paragraphs and figures as taught by the prior art and/or cited by the examiner while including in such consideration the cited prior art references in their entirety as potentially teaching all or part of the claimed invention. MPEP 2141.02 VI: “PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS." MPEP 2123 (I): “PATENTS ARE RELEVANT AS PRIOR ART FOR ALL THEY CONTAIN.”
Additionally, in an effort to provide a timely Office response to amendments the Applicant may file in response to this Office Action, it is respectfully requested that, on accompanying remarks/arguments papers, every effort be made to provide specific (page No., paragraph No., FIG. No., etc.) Specification/Drawings support for such amendments, particularly claim amendments.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim(s) 7-20 have been cancelled.
Response to Arguments
Applicant's arguments (hereinafter “arguments”) filed 3/6/2026 have been fully considered but they are not persuasive. In sum, the arguments, as found in at least page 8, allege that “the species restriction presented in the Restriction Requirement is improper for at least the reason that the species restriction defines groups of claims as species.” It is not that the species restriction defines groups of claims as species, the instant Application disclosure defines the mutually exclusive species and groups them into claims: species I, and the analysis thereof presented in the previous Office action, rests squarely on FIG. 3 and its supporting teachings in the specification; while species II, and the analysis thereof presented in the previous Office action, rests squarely on FIG. 6 and its supporting teachings in the specification; and lastly, species III, and the analysis thereof presented in the previous Office action, rests squarely on FIG. 7A and its supporting teachings in the specification. Under MPEP 806.04(f), “Claims to different species are mutually exclusive if one claim recites limitations disclosed for a first species but not a second, while a second claim recites limitations disclosed only for the second species and not the first. This may also be expressed by saying that to require restriction between claims limited to species, the claims must not overlap in scope. This is precisely the case here.
Therefore, the previous Restriction Requirement is still deemed proper and is therefore made FINAL.
Claim(s) 7-20 withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 3/6/26.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 6 and 27 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. It is claimed, in part: “wherein the one or more memory dies collectively have a first storage capacity.” There are any number of interpretations, any number of possible reads on “one or more memory dies.” The base claim, claim 1, does not provide an antecedent basis for the specific “one or more memory dies.” While in regard to claim 27, it is claimed, in part: “continuously store a copy of data written to the one or more volatile memory dies via the shared bus.” The Merriam-Webster Dictionary, 10th edition, defines “continuously” as without interruption or gaps, repeatedly without exceptions or reversals. In the relevant art, it is known, it is inherent that memory device will have interruptions, gaps in their operations; for example, one such interruption may be a power-down or sleep mode; according to the claim and giving it the broadest and reasonable interpretation, even during these events, data would still be “continuously” copied. This cannot be.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) (s) 1-3, 22-29 and 33 is/are rejected under 35 U.S.C. 102(a)(1) and/or 102(a)(2) as being anticipated by US 20220188606 to Roberts (“Roberts”).
As to claim 1, Roberts teaches A system-in-package (SiP) device (As found in at least the Abstract, at least [0034], and at least FIG. 1-6), comprising: a base substrate (As found in at least FIG. 6: 301); a processing unit carried by the base substrate (As found in at least FIG. 6: 103); and a combined high-bandwidth memory (HBM) device carried by the base substrate (As found in at least FIG. 6: 319, and at least [0098]-[0099]) and electrically coupled to the processing unit through one or more traces (As found in at least FIGS. 1-6: 309 and 109, wherein the combined HBM device comprises: an interface die (As found in at least FIG. 6: 311); one or more volatile memory dies carried by the interface die (As found in at least FIG. 6: 313/323, and at least [0117]); one or more non-volatile memory dies carried by the one or more volatile memory dies (As found in at least FIG. 6: 315/325, and at least [0046]: non-volatile memory: cross point memory; 325 as cross point in at least [0117]); and a shared bus electrically coupled to each of the interface die, the one or more volatile memory dies, and the one or more non-volatile memory dies (As found in at least [0088], [0092]).
As to claim 2, Roberts teaches wherein the shared bus includes a plurality of through substrate vias extending from the interface die to the one or more non-volatile memory dies (As found in at least [0088], [0092], [0111]).
As to claim 3, Roberts teaches the one or more volatile memory dies includes at least a first volatile memory die and a second volatile memory die (As found in at least FIG. 6: first and second 323 in first and second 319); and the plurality of through substrate vias includes at least a first subset of through substrate vias coupled between the interface die, the second volatile memory die, and the one or more non- volatile memory dies (As found in at least [0088], [0092], [0111], and at least FIGS. 1 and 6); and a second subset of through substrate vias, wherein: the first subset of through substrate vias is electrically coupled between the interface die, the first volatile memory die, and the one or more non- volatile memory dies (As found in at least [0088], [0092], [0111], and at least FIGS. 1 and 6).
As to claim 22, Roberts teaches wherein the interface die includes a memory controller (As found in at least FIG. 6: interface 311 includes controller 103; also see at least FIG. 1).
As to claim 23, Roberts teaches wherein the combined HBM device further comprises a second bus electrically coupled between the interface die and the one or more non- volatile memory dies, wherein the second bus is separate from the shared bus (As found in at least FIG. 6: there are at least two 319s, each having bus electrically coupling interface die 303 and memories).
As to claim 24-25, see rejection to at least claim 3; as found in at least FIGS. 1 and 6: bus 109, 119 and 309 communicate data un-down the 319s and across between the 319s and interface 303).
As to claim 26, Roberts teaches wherein the combined HBM device is configured to transfer a subset of data from the one or more non-volatile memory dies to the one or more volatile memory dies via the shared bus in response to a request from the processing unit (As found in at least [0080]: processing unit 103: “103 can be configured as a host of the memory device system. A memory controller in the memory interface 117 of the Deep Learning Accelerator 103 can be configured to fully schedule and orchestrate data movement in the memory device system”).
As to claim 27, Roberts teaches wherein the one or more non-volatile memory dies are configured to continuously store a copy of data written to the one or more volatile memory dies via the shared bus (As found in at least [0093]: copy data to or from the memory 323 (non-volatile) and 325 (volatile) within the memory stack 319).
As to claim(s) 28-29, see rejection to at least claim(s) 1 and 3.
As to claim 33, see rejection to at least claim(s) 1 and 22.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20220188606 to Roberts (“Roberts”) in view of U.S. Patent/Publication No. 20210391303 to Lung (“Lung”).
As to claim 4, Roberts teaches substantially the claimed invention, though it may not include expressly: a controller die carried by the interface die beneath the one or more volatile memory dies; and one or more auxiliary through substrate vias extending between the interface die and the controller die.
However, relevantly and complementarily, Lung teaches: a controller die carried by the interface die beneath the one or more volatile memory dies; and one or more auxiliary through substrate vias extending between the interface die and the controller die (As found in at least FIG. 2: substrate 110, interface die 120, controller die 130, volatile memories 150 and non-volatile memories 160; and vias extending between 120 and 130).
Roberts and Lung are analogous art because they are from the same field of endeavor, and/or are reasonably pertinent to the inventor’s problem to be solved: memory device stacks that may include plurality of types of memories over control and substrate.
At the time of invention, it would have been obvious to a person of ordinary skill in the art to complement the teachings of Roberts as set forth in this Office action and as found in the reference with the relevant and complementary teachings of Lung also as set forth in this Office action and as found in the reference(s). The suggestion/motivation would have been obvious to one of ordinary skill in the art before the effective filing date of the present Application: Roberts teaches an interface die 311 that also includes controlling operations built in 307; while Lung expressly teaches a controller die over an interface die, as set forth in the reference and cited above; either solution is optimal according to the specific application that is to be implemented.
Therefore, it would have been obvious to combine Roberts with Lung to make the above modification.
Claim(s) 5 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20220188606 to Roberts (“Roberts”) in view of U.S. Patent/Publication No. 10719445 to Navon et al. (“Navon”).
As to claim 5, Navon complements the teachings found in Robert’s by including: one or more non-volatile memory dies are configured to provide non-volatile copy of data stored in the one or more memory dies accessible to the one or more volatile memory dies via the shared bus in response to a power-up request (As found in at least Column 33, lines 7-15).
Roberts and Lung are analogous art because they are from the same field of endeavor, and/or are reasonably pertinent to the inventor’s problem to be solved: memory device that may include plurality of types of memories.
At the time of invention, it would have been obvious to a person of ordinary skill in the art to complement the teachings of Roberts as set forth in this Office action and as found in the reference with the relevant and complementary teachings of Navon also as set forth in this Office action and as found in the reference(s). The suggestion/motivation would have been obvious to one of ordinary skill in the art before the effective filing date of the present Application: data may be stored in non-volatile memory (un affected by loss of power); while upon power-up such data may be copied to volatile memory (low latency memory, but affected by loss of power).
Therefore, it would have been obvious to combine Roberts with Navon to make the above modification.
As to claim 21, Navon teaches wherein the one or more non-volatile memory dies are configured to store a state of the one or more volatile memory dies in response to a power-down request (As found in at least Column 4, lines 60-63: data in volatile memory (smaller data structure) is stored in non-volatile memory in power down; as found in at least Column 33, lines 40-43 further provide support for the smaller data structure including volatile memory such as RAM 116).
Claim(s) 30-32 and 34 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20220188606 to Roberts (“Roberts”) in view of U.S. Patent/Publication No. 20210210500 to Lin (“Lin”).
As to claim 30, while Roberts teaches substantially the claimed invention, the teachings may not expressly include: wherein the one or more volatile memory dies are selectively coupled to the plurality of first through substrate vias.
Yet, relevantly and complementarily, Lin teaches wherein the one or more volatile memory dies are selectively coupled to the plurality of first through substrate vias (As found in at least FIG. 3 and [0033]: For example, the direct inter-die connections 312, similar to the direct inter-die connections 212 of FIG. 2, may allow the controller die 302 to directly communicate with one or more of the volatile memory dies 306 and/or the NV memory die 304. That is, the connectivity is selectively with one volatile or NV memory or more of these memories).
Roberts and Lin are analogous art because they are from the same field of endeavor, and/or are reasonably pertinent to the inventor’s problem to be solved: memory device that may include plurality of types of memories.
At the time of invention, it would have been obvious to a person of ordinary skill in the art to complement the teachings of Roberts as set forth in this Office action and as found in the reference with the relevant and complementary teachings of Lin also as set forth in this Office action and as found in the reference(s). The suggestion/motivation would have been obvious to one of ordinary skill in the art before the effective filing date of the present Application: given a stack of memories, the options are (1) communicate with all of them at once, (2) selectively communicate with one or more at any given time; it is clear and obvious that option (2) is more desirable: lower power consumption, lower chip noise (not all memories are being accessed), and more.
Therefore, it would have been obvious to combine Roberts with Lin to make the above modification.
As to claim 31, Roberts and Lin teach wherein the one or more non-volatile memory dies are electrically coupled to each of the plurality of second through substrate vias (In Roberts, see at least the rejection to claim 3; while Lin in at least FIGS. 2-3 teach NV memories 204, 304 connected to through substrate vias 310, 312).
As to claim 32, at least Lin teaches wherein the first bus is configured to communicate data between the interface die and the one or more volatile memory dies while the second bus is configured to simultaneously communicate data between the interface die and the one or more non-volatile memory dies (As found in at least FIGS. 2-3: first bus such as 310 to connect to volatile memories, second bus such as 312 to connect to NV memories).
As to claim 34, Lin teaches the plurality of volatile memory dies includes at least a first volatile memory die and a second volatile memory die (As found in at least FIG. 3: 306); the plurality of TSVs are organized into subgroups including at least a first subgroup and a second subgroup (As found in at least FIG. 3: groups 310, 308, 312); the first subgroup is selectively coupled to the first volatile memory die (As found in at least FIG. 3: 310 to couple to volatile memories 306); and the second subgroup is selectively coupled to the second volatile memory die (As found in at least FIG. 3: 312 to couple to one or more of 306).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO N HIDALGO whose telephone number is (571)270-3306. The examiner can normally be reached M-F 9:00-7:30 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 5712721852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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FERNANDO N. HIDALGO
Primary Examiner
Art Unit 2827
/Fernando Hidalgo/ Primary Examiner, Art Unit 2827