DETAILED ACTION
This non-final action is responsive to communications: application filed on 06/20/2024.
Claims 1-20 are pending. Claims 1, 14, and 17 are independent.
Examiner Notes
A) Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. B) Per MPEP 2173.04 “If the claim is too broad because it reads on the prior art, a rejection under either 35 U.S.C. 102 or 103 would be appropriate”. C) Examiner cites particular paragraphs or columns and lines in the references as applied to Applicant's claims for the convenience of the Applicant. Other passages and figures may apply as well. Per MPEP 2141.02 VI prior art must be considered in its entirety. D) Per MPEP 2112 and 2112 V, express, implicit, and inherent disclosures of a prior art reference may be relied upon in the rejection of claims under 35 U.S.C. 102 or 103.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Domestic Priority
3. See ADS for domestic priority details.
No Information Disclosure Statement
4. No IDS has been filed as of this office action date.
Claim Rejections - 35 USC § 102
5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
6. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
7. Claims 1-5, 10, and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Do et al. (US 2021/0225425 A1).
Regarding independent claim 1, Do teaches an apparatus (Fig. 1: 10 system/ memory device. See Examiner’s Markup Version of Figure 7. See Fig. 1-Fig. 15 for illustrated components and functionality) comprising:
a plurality of first regions (Fig. 7: R1. These are Block specific circuitry regions) arranged in a first direction (Fig. 7: x-direction),
each of the plurality of first regions including a second region (Fig. 7: R1 and 2060 common region) and a third region (Fig. 7: R1 and 2005 common region);
a plurality of main word lines (para [0051], Fig. 15: MWLs) extending in a second direction crossing the first direction (Fig. 7: MWLs extend in y-direction) and arranged in the first direction (Fig. 7: MWLs arranged in x-direction);
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a plurality of main word driver circuits (Fig. 7: MWDs. See also Fig. 15: MWD) each configured to activate an associated one of the plurality of main word lines (Fig. 15: MWL) responsive to a row address signal (para [0051]); and
a voltage control circuit (Fig. 7: 2005) configured to supply a first power voltage to the plurality of main word driver circuits in a first operation mode (Fig. 7, Fig. 15, para [0059]: VPP “high voltage” used in active mode) and a second power voltage different from the first power voltage to the plurality of main word driver circuits in a second operation mode (Fig. 7, Fig. 15, para [0059]: VPPIB “lower high voltage” used in standby mode),
wherein one or ones of the plurality of main word driver circuits (Fig. 7: MWDs) is arranged in the second region (Fig. 7: R1 and 2060 common region) included in each of the plurality of first regions (Fig. 7: R1), and
wherein the voltage control circuit (Fig. 7: 2005) is divided into multiple circuit portions which are arranged in two or more third regions (Fig. 7: 730i-7301. See Fig. 15: regions of 730 with each MWD) in two or more of the plurality of first regions (Fig. 7: R1), respectively.
Regarding claim 2, Do teaches the apparatus of claim 1, wherein the voltage control circuit includes:
a first switch circuit (Fig. 15: 901) coupled between a first power line supplied with the first power voltage (Fig. 15: VPP) and a third power line supplying an operation voltage (Fig. 15: VSS) to the plurality of main word driver circuits (Fig. 15: MWD. See also Fig. 7);
a second switch circuit (Fig. 15: 902) coupled between a second power line supplied with the second power voltage (Fig. 15: VPPIB) and the third power line (Fig. 15: VSS); and
a control circuit configured to control the first and second switch circuits (Fig. 15 in context of para [0098]: PBLS control line and associated circuitry),
wherein the first switch circuit (Fig. 15: 901) is arranged in the third region (Fig. 15: regions of 730 with each MWD) included in a first one of the plurality of first regions (Fig. 7: R1), and
wherein the control circuit is arranged in the third region (Fig. 15: PBLS control line and associated circuitry is located in 730) included in a second one of the plurality of first regions (Fig. 7: PBLS control line would be located in all R1 regions and thus the limitation is satisfied).
Regarding claim 3, Do teaches the apparatus of claim 2, wherein the second switch circuit (Fig. 15: 902) is arranged in the third region (Fig. 15: PBLS control line and associated circuitry is located in 730) included in the second one of the plurality of first regions (Fig. 7: PBLS control line would be located in all R1 regions and thus the limitation is satisfied).
Regarding claim 4, Do teaches the apparatus of claim 3, wherein the voltage control circuit further includes a third switch circuit coupled in parallel with the first switch circuit, and wherein the third switch circuit is arranged in the third region included in a third one of the plurality of first regions (Fig. 15: 901 located in another Fig. 7: R1 region)
Regarding claim 5, Do teaches the apparatus of claim 4, wherein the second one of the plurality of first regions is arranged between the first one of the plurality of first regions and the third one of the plurality of first regions in the first direction (see Fig. 7 arrangement).
Regarding claim 10, Do teaches the apparatus of claim 2, further comprising: a memory cell array (Fig. 7: 2080) coupled to the plurality of main word lines (Fig. 7: MWDs) and located so as to overlap the plurality of first regions in the second direction (Fig. 7: overlaps R1 in both x, y direction); and
a fourth region (Fig. 7: 710) located adjacent to the plurality of first regions in the first direction (Fig. 7: y-direction) so as not to overlap the memory cell array in the second direction (Fig. 7: 710 does not overlap with 2080).
Regarding independent claim 17, Do teaches an apparatus (Fig. 1: 10 system/ memory device. See Fig. 7: Examiner’s Markup version of Figure 7. See Fig. 1-Fig. 15 for illustrated components and functionality) comprising:
a plurality of first regions (Fig. 7: R1. These are Block specific circuitry regions) arranged in line (Fig. 7: x-direction in linear fashion),
each of the plurality of first regions (Fig. 7: R1) including
a second region in a center area (Fig. 15: 536, 524 region. See in relation to Fig. 7),
a third region along a first side (Fig. 15: 730 region. See in relation to Fig. 7) and a fourth region along a second side (Fig. 15: 537, 538 region. See in relation to Fig. 7) opposed to the first side (See in relation to Fig. 7);
a plurality of main word driver circuits (Fig. 7: MWDs) each arranged in a corresponding one of second regions (Fig. 15: 536, 524 region) of the plurality of first regions (Fig. 7: R1); and
a voltage control circuit (Fig. 7: 2005) configured to supply a voltage to each of the plurality of main word driver circuits (Fig. 7: MWDs),
the voltage control circuit (Fig. 7: 2005. See Fig. 15) is divided into multiple circuit portions (Fig. 15: 730 portion and 537, 538 portion) which are arranged in one or ones of the third (Fig. 15: 730 region) and fourth regions (Fig. 15: 537, 538 region) in one or ones of the plurality of first regions (Fig. 7: R1).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
8. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
9. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
10. Claims 14-15 is/are rejected under 35 U.S.C. 103 as being obvious over NOGUCHI (US 2012/0320699 A1), in view of Do et al. (US 2021/0225425 A1).
Regarding independent claim 14, teaches an apparatus (para [0064], Fig. 2: 101. See Examiner’s Markup version of NOGUCHI Figure 2. See Fig. 1-Fig. 9 for illustrated components and functionality) comprising:
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a memory cell array (Fig. 2 1012) configured to be accessed by a plurality of main word signals (Fig. 2: MWL_k);
a main word circuit (Fig. 2: 1022) configured to activate one of the plurality of main word signals (Fig. 2: MWL_k) and arranged in a main word circuit region (Fig. 2: MWD region) overlapping with the memory cell array in a first direction (See Fig. 2: x-direction)
a sense circuit (Fig. 2: SAMP) configured to amplify a read data read from the memory cell array (para [0065]) and arranged in a sense amplifier region (Fig. 2: SAMP region) overlapping with the memory cell array in a second direction (Fig. 2: x-direction); and
a voltage control circuit (Fig. 2: voltage control switches in row decoder) configured to control an operation voltage of the main word circuit (operation of MWD),
wherein a part of the voltage control circuit (Fig. 2: voltage control switches in MWD) is arranged in the main word circuit region (Fig. 2: MWD region) so as to overlap with the memory cell array in the first direction (Fig. 2: y-direction), and
wherein another part of the voltage control circuit (Fig. 2: 1021. Para [0067]) is arranged in a gap region (Fig. 2: corner portion of row decoder) adjacent to the main word circuit region (Fig. 2: MWD region) in the second direction (Fig. 2: x-direction) and
adjacent to the sense amplifier region (Fig. 2: SAMP region) in the first direction (Fig. 2: y-direction) so as not to overlap with the memory cell array in the first direction (Fig. 2: 1021 does not overlap with memory array).
NOGUCHI is silent with respect to voltage control circuit configured to control operation voltage of the main word circuit, wherein a part of the voltage control circuit is arranged in the main word circuit region so as to overlap with the memory cell array.
Do teaches –
a voltage control circuit (Fig. 7: 2005 and Fig. 15: 537, 538 combined) configured to control an operation voltage of the main word circuit (Fig. 7 in context of para [0059]: supplies VPP “high voltage” in active mode and VPPIB “lower high voltage” in standby mode),
wherein a part of the voltage control circuit (Fig. 15: 537, 538) is arranged in the main word circuit region (Fig. 7, Fig. 15: MWD region) so as to overlap with the memory cell array.
Both NOGUCHI and Do are in the same field of endeavor of DRAM word line driving circuitry structure and associated device performance and they are in the analogous field of art.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine Do's main word line driver circuitry and layout into the apparatus of NOGUCHI such that voltage control circuit with enhanced components and functionality can be implemented in order to improve device reliability “…reduces gate stress…” (Do para [0005]).
Regarding claim 15, NOGUCHI and Do teach the apparatus of claim 14. Do teaches wherein the voltage control circuit includes:
a plurality of first power circuits (Fig. 15: 901, 537, 538 combined) configured to supply the operation voltage having a first level to the main word circuit (Fig. 15: VPP); and
a second power circuit (Fig. 15: 902) configured to supply the operation voltage having a second level lower than the first level to the main word circuit (Fig. 15: VPPIB, para [0059]),
wherein one of the plurality of first power circuits (Fig. 15: 537, 538 portion) is arranged in the main word circuit region (Fig. 15: MWD region), and wherein another of the plurality of first power circuits (Fig. 15: 901 portion) is arranged in the gap region (Fig. 7: 730, Fig. 15: 730).
Allowable Subject Matter
Claims 6-9, 11-13, 16, and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claims listed, the prior art of record does not appear to teach, suggest, or provide motivation for combination for the following limitations of the claims:
Claims 6-9. The apparatus of claim 2, further comprising: a first decoder circuit configured to decode a first part of the row address signal to activate one of a plurality of first selection signals; and a first level shift circuit configured to convert a level of the plurality of first selection signals from a first amplitude to a second amplitude, wherein the first level shift circuit is arranged in the third region included in a fourth one of the plurality of first regions.
Claim 11. The apparatus of claim 10, wherein the voltage control circuit is arranged in the third region included in one or ones of the plurality of first regions without arranged in the fourth region.
Claim 12. The apparatus of claim 10, wherein the voltage control circuit further includes a third switch circuit coupled in parallel with the first switch circuit, and wherein the third switch circuit is arranged in the fourth region.
Claims 16. The apparatus of claim 15, wherein the voltage control circuit further includes a control circuit configured to activate the first power circuit or the second power circuit, and wherein the control circuit is arranged in the main word circuit region.
Claim 18. The apparatus of claim 17, wherein the third region is only available for a first conductivity type transistor, and wherein the fourth region is only available for a second conductivity type transistor.
Claims 19-20. The apparatus of claim 17, wherein the multiple circuit portions includes: a first switch circuit configured to supply a first voltage to each of the plurality of main word driver circuits; a second switch circuit configured to supply a second voltage to each of the plurality of main word driver circuits; and a control circuit configured to control the first and second switch circuits, wherein the first switch circuit is arranged in one of the third regions, wherein the second switch circuit is arranged in another one of the third regions, wherein a part of the control circuit is arranged in one of the fourth regions, wherein another part of the control circuit is arranged in the another one of the third regions.
Prior Art Not Relied Upon
The prior art made of record and not relied upon (MPEP § 707.05) is considered pertinent to applicant's disclosure: Park (US 2021/0327490 A1): Fig. 1-Fig. 9 disclosure applicable for all claims. Schreck (US 2023/0223069 A1): Fig. 1-Fig. 8 disclosure applicable for all claims.
Conclusion
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/MUSHFIQUE SIDDIQUE/Primary Examiner, Art Unit 2825