DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 8-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yamagata et al. (US Pat. 6,310,815) in view of Fujisawa et al. (US Pat. 6,195,305).
Regarding claims 1, 3, 16, and 20 Fig. 40 of Yamagata discloses an apparatus comprising:
a first memory mat [215a];
first [220a] and second [220b] sense amplifier regions arranged such that the first memory mat [215a] is sandwiched between the first [220a] and second [220b] sense amplifier regions in a first direction [vertical], the first sense amplifier region [220a] including a first sense amplifier [SENSE AMPLIFIER 220a], and the second sense amplifier region including a second sense amplifier [SENSE AMPLIFIER 220b]; and
first [224a] and second [224b] array control circuit regions arranged in the first direction [vertical], the first array control circuit region including a first array control circuit [SENSE CONTROL] configured to control the first sense amplifier [by applying control signal LSA and voltage to sense amplifier, as shows in Fig. 42], and the second array control circuit region including a second array control circuit [SENSE CONTROL of 24b] configured to control the second sense amplifier [220b].
Yamagata discloses all claimed invention, but does not specifically show a well region, and thus does not show wherein each of the first and second array control circuit regions includes a first well region of a first conductivity type in which a first circuit part of each of the first and second array control circuits are arranged, respectively, and wherein the first well region of the first array control circuit region and the first well region of the second array control circuit region are integrated. However, Fig. 10 of Fujisawa discloses a memory device having shared sense amplifier arrangement, wherein each of the first [region A (CROSS AREA) 18 for top sense amplifier SA, as shows in Fig. 9, CROSS AREA A applies voltages VDL, VDD, and VSS to sense amplifier. Therefore, it can be considered SA control circuit] and second [region A (CROSS AREA) 18 for the SA below first SA] array control circuit regions includes a first well region [NWELL] of a first conductivity type [N-type] in which a first circuit part of each of the first and second array control circuits are arranged [both first and second control circuits are arranged in NWELL], respectively, and wherein the first well region of the first array control circuit region and the first well region of the second array control circuit region are integrated [they both are integrated in the memory circuit, which Fig. 6 shows that all well regions are integrated on substrate PSUB, but are isolated from the substrate].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Fujisawa’s memory device with shared amplifier to the teachings of Yamagata’s memory device with shared amplifier such that Yamagata’s shared amplifiers with sense controller arranged in well region according to Fujisawa’s teachings for the purpose of reducing power-consumption without reducing reliability [col. 2, lines 10 to 14].
Regarding claim 2, Fig. 40 of Yamagata discloses wherein a layout of the first circuit part of the first array control circuit [224a] and a layout of the first circuit part of the second array control circuit [224b] are arranged symmetrically with respect to a boundary [can be ROW DECODER 222a] between the first and second array control circuit regions.
Regarding claim 8, Fig. 40 of Yamagata discloses a third sense amplifier region [220c] including a third sense amplifier [SENSE AMPLIFIER]; a second memory mat [215B] arranged between the second [220B] and third [220c] sense amplifier regions in the first direction; and a third array control circuit region [224c] including a third array control circuit [SENSE CONTROL] configured to control the third sense amplifier [220c], wherein a layout of the second array control circuit [224b] and a layout of the third array control circuit [224c] are arranged symmetrically in the first direction [vertical].
Regarding claim 9, Fig. 33 and Fig. 40 of Yamagata discloses wherein the first memory mat includes first and second digit lines [2 of signals, 5x] extending in the first direction [vertical], wherein the second memory mat includes third and fourth digit lines [another two of 5x signals] extending in the first direction [vertical], wherein the first sense amplifier is coupled to the first digit line, wherein the second sense amplifier is coupled to the second and third digit lines [second sense amplifier is connected to digit lines of second memory array], and wherein the third sense amplifier [220c] is coupled to the fourth digit line [one of the signal line 5x].
Regarding claims 10 and 18, Fig. 39 of Yamagata discloses a first word driver circuit [220a] configured to activate a first word line [WL] included in the first memory mat [215a] and extending in a second direction [horizontal] perpendicular to the first direction [vertical]; a second word driver circuit [222b] configured to activate a second word line included in the second memory mat [215b] and extending in the second direction; and a word control circuit [each word driver circuit comprises a controller (NAND gate 230ba). Therefore, a word control circuit is a combination of each NAND GATE from each driver] configured to control the first [230ba controls first driver, and another NAND GATE from driver 222b controls second word driver] and second word driver circuits, wherein the word control circuit is arranged between the second and third array control circuit regions in the first direction [vertical].
Regarding claim 11, Fig.40 of Yamagata discloses a fourth sense amplifier region [220m] including a fourth sense amplifier [SENSE AMPLIFIER]; a third memory mat [between 220c and 220m] arranged between the third [220c] and fourth [220m] sense amplifier regions in the first direction; and a fourth array control circuit region [224m] including a fourth array control circuit configured to control the fourth sense amplifier, wherein a layout of the third array control circuit [224c] and a layout of the fourth array control circuit [224m] are arranged symmetrically in the first direction [vertical].
Regarding claims 12 and 17, Yamagata discloses all claimed invention, but does not specifically disclose wherein each of the third and fourth array control circuit regions includes a first well region of the first conductivity type in which a first circuit part of each of the third and fourth array control circuits are arranged, respectively, and wherein the first well region of the third array control circuit region and the first well region of the fourth array control circuit region are integrated. However, Fig. 10 of Fujisawa discloses all sense amplifier [SA] and the corresponding controller [A (CROSS AREA) 18] are arranged in NWELL, which are integrated.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Fujisawa’s memory device with shared amplifier to the teachings of Yamagata’s memory device with shared amplifier such that Yamagata’s shared amplifiers with sense controller arranged in well region according to Fujisawa’s teachings for the purpose of reducing power-consumption without reducing reliability [col. 2, lines 10 to 14].
Regarding claim 13, Fig. 39 and Fig. 40 of Yamagata discloses an additional circuit region arranged [within region 210b] between the third and fourth array control circuit regions.
Regarding claim 14, Fig. 39 and Fig. 43 of Yamagata discloses wherein the additional circuit region includes a compensation capacitor [DCP in Fig. 43].
Regarding claim 15, Fig. 40 of Yamagata discloses apparatus comprising:
first [220a], second [220b], third [220c], and fourth [220m] sense amplifiers arranged in a first direction [vertical] in this order;
a first memory mat [215a] arranged between the first [220a] and second [220b] sense amplifiers;
a second memory mat [215b] arranged between the second [220b] and third [220c] sense amplifiers;
a third memory mat arranged between the third [220c] and fourth sense amplifiers [220m]; and
first, second, third, and fourth array control circuits [224a, 224b, 224c, 224m] each configured to control the first, second, third, and fourth sense amplifiers [220a, 220b, 220c, and 220m], respectively,
wherein the first, second, third, and fourth array control circuits [224a, 224b, 224c, 224m] and the first, second, third, and fourth sense amplifiers [220a, 220b, 220c, and 220m] are arranged in a second direction [horizontal] perpendicular to the first direction, respectively,
wherein a layout of the first array control circuit and a layout of the second array control circuit [224a and 224b] are arranged symmetrically in the first direction [vertical],
wherein a layout of the second array control circuit [224b] and a layout of the third array control circuit [224c] are arranged symmetrically in the first direction [vertical], and
wherein a layout of the third array control circuit [224c] and a layout of the fourth array control circuit [220m] are arranged symmetrically in the first direction.
Regarding claim 19, Fig. 40 of Yamagata discloses an apparatus comprising:
first, second, third, and fourth sense amplifiers [220a, 220b, 220c, 220m] arranged in a first direction [vertical] in this order;
a first memory mat [215a] arranged between the first [220a] and second [220b] sense amplifiers;
a second memory mat [215b] arranged between the second [220b] and third [220c] sense amplifiers;
a third memory mat arranged between the third [220c] and fourth [220m] sense amplifiers;
first, second, third, and fourth array control circuits [224a, 224b, 224c, 224m] each configured to control the first, second, third, and fourth sense amplifiers [220a, 220b, 220c, 220m], respectively;
first, second, and third word driver circuits [222a, 222b, 222c (between 224c and 224m) assigned to the first, second, and third memory mats, respectively;
a word control circuit [each driver has control circuit (NAND gate shows in Fig. 41) configured to control the first, second, and third word driver circuits [drivers 230ab and more]; and
a compensation capacitor [DCP in Fig. 43],
wherein the first, second, third, and fourth [224a, 224b, 224c, and 224m] array control circuits and the first, second, third, and fourth sense amplifiers [220a, 220b, 220c, and 220m] are arranged in a second direction [horizontal] perpendicular to the first direction, respectively,
wherein a layout of the first array control circuit [224a] and a layout of the second array control circuit [224b] are arranged symmetrically [reflection through circuit 222a] in the first direction,
wherein a layout of the third array control circuit [224c] and a layout of the fourth array control circuit [224m] are arranged symmetrically in the first direction,
wherein the word control circuit [NAND gate of driver shows in Fig. 41] is arranged between the second [224b] and third [224c] array control circuits, and wherein the compensation capacitor [DCP, Fig. 43, as discloses in col. 41, lines 22 to 30, the compensation capacitor is arranged in region 210b, which is a region between two row decoders. Therefore, the capacitor can be arranged between two row decoders 220a and 220b, which is also between first and second array control circuits 224a and 224b] is arranged between the first and second array control circuits.
Allowable Subject Matter
Claims 4-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 4-7, the prior art does not teach or suggest either alone or in combination wherein each of the first and second array control circuit regions further includes a second well region of a second conductivity type opposite to the first conductivity type, and wherein the first well regions of the first and second array control circuit regions are surrounded by the second well regions of the first and second array control circuit regions in a plan view.
Conclusion
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/ANTHAN TRAN/Primary Examiner, Art Unit 2825