Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
METHOD FOR MANUFACTURING A CONTACT PLUG FOR SEMICONDUCTOR DEVICE
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5, 9-12 and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. [US PGPUG 20150147880] (hereinafter Lee).
Regarding claim 1, Lee teaches a method for manufacturing a semiconductor device, the method comprising:
forming an interlayer dielectric film (304, Para 40) having a contact hole (420, Para 49, Fig. 15) above a semiconductor substrate (302. Para 40, Fig. 15);
forming an initial metal film (406, Para 50) containing a predetermined first metal on an upper surface of the semiconductor substrate and on side walls of the interlayer dielectric film in the contact hole (Para 50, Fig. 16);
forming a first alloy layer (308, Para 51) containing the first metal (Para 50) on the upper surface of the semiconductor substrate (Para 51, Fig. 17; wherein silicide 308 is formed by annealing metal layer 406);
forming a first barrier metal portion (310, Para 44) containing the first metal on the side walls of the interlayer dielectric film (Fig. 21);
etching at least one of the initial metal film or the first barrier metal portion in the contact hole (Para 52, Fig. 18);
forming an oxide layer (304, Para 53, silicon oxide) on an upper surface of the first alloy layer in the contact hole (Fig. 19);
etching the oxide layer in the contact hole (Para 54, Fig. 20);
forming a second barrier metal portion (312, Para 45), which is conductive (Para 45), above the first alloy layer in the contact hole (Fig. 23); and
forming a plug layer (314, Para 45) above the second barrier metal portion in the contact hole (Fig. 23).
Regarding claim 2, Lee teaches a method for manufacturing a semiconductor device wherein the forming the first alloy layer includes annealing the initial metal film provided on the upper surface of the semiconductor substrate (Para 51).
Regarding claim 3, Lee teaches a method for manufacturing a semiconductor device wherein n the forming the first barrier metal portion includes annealing the initial metal film provided on the side walls of the interlayer dielectric film (Fig. 15-21; i.e., in view of the fact that annealing of the initial metal film provided on the side walls of the interlayer dielectric film is a process that led to the effective forming of the first barrier metal).
Regarding claim 5, Lee teaches a method for manufacturing a semiconductor, the method comprising etching the initial metal film, which has remained, in the contact hole after the forming the first alloy layer and before the forming the second barrier metal portion (Para 51/52, Fig. 17-18).
Regarding claim 9, Lee teaches a method for manufacturing a semiconductor device wherein the etching the oxide layer includes dry etching the oxide layer (Para 54).
Regarding claim 10, Lee teaches a method for manufacturing a semiconductor device wherein in the etching the oxide layer, the oxide layer is etched until the upper surface of the first alloy layer is exposed (Para 54).
Regarding claim 11, Lee teaches a method for manufacturing a semiconductor device wherein in the etching the oxide layer, the oxide layer is thinned, and etched such that the oxide layer remains on the upper surface of the first alloy layer (Fig. 20).
Regarding claim 12, Lee teaches a method for manufacturing a semiconductor device wherein the oxide layer is selectively provided using a mask provided above the semiconductor substrate (Fig. 18-19; wherein in forming the oxide layer, portions of interlayer dielectric film 304 remaining on the surface of the substrate functions as a mask).
Regarding claim 21, Lee teaches a method for manufacturing a semiconductor device, the method comprising:
forming an interlayer dielectric film (304, Para 40) having a contact hole (420, Para 49, Fig. 15) above a semiconductor substrate (302. Para 40, Fig. 15);
forming an initial metal film (406, Para 50) containing a predetermined first metal on an upper surface of the semiconductor substrate and on side walls of the interlayer dielectric film in the contact hole (Para 50, Fig. 16);
forming a first alloy layer (308, Para 51) containing the first metal on the upper surface of the semiconductor substrate (Para 51, Fig. 17; wherein silicide 308 is formed by annealing metal layer 406);
etching the initial metal film in the contact hole (Para 52, Fig. 18);
forming an oxide layer (304, Para 53, silicon oxide) on an upper surface of the first alloy layer in the contact hole (Fig. 19);
etching the oxide layer in the contact hole (Para 54, Fig. 20);
forming a second barrier metal portion (310, Para 44), which is conductive (TiN, Para 44), above the first alloy layer in the contact hole (Fig. 21); and
forming a plug layer (315, Para 45) above the second barrier metal portion in the contact hole (Fig. 23).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Chua et al. [US PGPUB 20080119057] (hereinafter Chua).
Regarding claim 4, Lee teaches the limitation of claim 1 upon which it depends.
Lee does not specifically disclose a method for manufacturing a semiconductor device wherein the forming the oxide layer includes annealing the semiconductor substrate in an oxygen atmosphere.
Referring to the invention of Chua, Chua teaches forming the silicon oxide layer by annealing a semiconductor substrate in an oxygen atmosphere (Para 10).
In view of such teaching by Chua, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the invention of Lee comprise the teaching of Chua at least based on the rationale of using known technique to improve similar devices (methods, or products) in the same way using (MPEP 2143.I.C).
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Chiang [US PGPUB 20050151180].
Regarding claim 7, Lee teaches the limitation of claim 1 upon which it depends.
Lee does not specifically disclose a method for manufacturing a semiconductor device wherein the etching the oxide layer includes wet etching the oxide layer.
Referring to the invention of Chiang, Chiang discloses etching of silicon oxide layer 2 either via wet etch procedures using a buffered hydrofluoric acid solution or via a dry etch procedure using CHF.sub.3 as an etchant (Para 16).
In view of such teaching by Chiang, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the invention of Lee comprise the teachings of Chiang at least based on the rationale of simple substitution of one known element/structure with a suitable another to obtain predictable results (MPEP 2143.I.B) or using known technique to improve similar devices (methods, or products) in the same way using (MPEP 2143.I.C).
Regarding claim 8, the modified invention of Lee specifically in view of Chiang teaches a method for manufacturing a semiconductor device wherein a chemical liquid for the wet etching is hydrogen peroxide or buffered hydrofluoric acid (Para 16).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Kudo [US PGPUB 20230282735].
Regarding claim 18, Lee teaches the limitation of claim 1 upon which it depends.
Lee does not specifically disclose a method for manufacturing a semiconductor device, the method comprising forming a trench contact portion which has the contact hole and extends from a front surface of the semiconductor substrate in a depth direction of the semiconductor substrate.
Referring to the invention of Kudo, Kudo discloses a trench contact portion which has the contact hole (Fig. 24, i.e., region in which material BM/CF are formed) and extends from a front surface of the semiconductor substrate in a depth direction of the semiconductor substrate (Fig. 24).
In view of such teaching by Kudo, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the invention of Lee comprise the teaching od Kudo in order to an increased contact surface area and thus improve electrical characteristics of the device.
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Soeno [US PGPUB 20140077253].
Regarding claim 19, Lee teaches the limitation of claim 1 upon which it depends.
Lee does not specifically disclose a method for manufacturing a semiconductor device, the method comprising forming a front surface side lifetime control region on a front surface side with respect to a center of the semiconductor substrate in a depth direction of the semiconductor substrate.
Referring to the invention of Soeno, Soeno teaches a contact structure 131/141 (Para 35) of a device, wherein the device comprises forming a front surface side lifetime control region (115, Para 37) on a front surface side with respect to a center of the semiconductor substrate in a depth direction of the semiconductor substrate (Fig. 2).
In view of such teaching by Soeno, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the device of Lee implemented with the structure of Soeno at least based on the rationale of simple substitution of one known element/structure with a suitable another to obtain predictable results (MPEP 2143.I.B) or combining prior art elements according to known methods to yield predictable results (MPEP 2143.I.A).
Referring claim 20, the modified invention of Lee specifically in view of Soeno teaches a method for manufacturing a semiconductor device wherein the front surface side lifetime control region is formed by irradiating the semiconductor substrate with a particle beam (Para 53).
Allowable Subject Matter
Claims 6 and 13-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/ISMAIL A MUSE/ Primary Examiner, Art Unit 2812
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