DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the limitation in claim 17 “the via does not penetrate the second doped region” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1 recites "a word line structure provided adjacent to the first surface, and a first doped region and a second doped region located in the substrate and separated from each other". In the description, the functions of the word line, the first doped region, and the second doped region are unknown. In addition, the description may include a case where it is not a MOS transistor in which "the word line is a gate electrode, and the doped region 104 and the doped region 106 are a source region and a drain region, respectively" in the detailed description of the invention (¶0030- ¶0031), and Fig. 1). In such a case, it is not specifically described in the detailed description of the invention, and it cannot be recognized that it is described in the detailed description of the invention. The same applies to the inventions according to Claims 2-20 depending on Claim 1.
Where applicant acts as his or her own lexicographer to specifically define a term of a claim contrary to its ordinary meaning, the written description must clearly redefine the claim term and set forth the uncommon definition so as to put one reasonably skilled in the art on notice that the applicant intended to redefine that claim term. Process Control Corp. v. HydReclaim Corp., 190 F.3d 1350, 1357, 52 USPQ2d 1029, 1033 (Fed. Cir. 1999). The term “cylindrical shape” in claim 15 is used by the claim to mean “elongated rectangular shape” while the accepted meaning is “elongated object with two parallel sides .” The term is indefinite because the specification does not clearly redefine the term.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Roh et al. (Pg Pub US 20230187352 A1).
Regarding claim 1, Roh teaches a dynamic random access memory structure (fig 2b: 1000), comprising:
a substrate (¶0021, fig 2B:101), comprising a first surface (¶0021, fig 2B: F1) and a second surface (¶0021, fig 2B: F2) opposite to each other;
a word line structure (¶0023, fig 2B: WL), disposed adjacent to the first surface (¶0021, fig 2B: F1) (fig 2B: WL disposed adjacent to 101);
a first doped region (¶0025, fig 2b: 2a first impurity region) and a second doped region (¶0025, fig 2b: 2b second impurity region), located in the substrate (¶0021, fig 2B:101) and separated from each other (¶0025, fig 2b: 2a and 2b located in 101 and opposite from each other);
a capacitor structure (¶0036, fig 2b: Cap1), located on the first surface (¶0021, fig 2B: F1) and electrically connected to the first doped region (¶0025, fig 2b: 2a first impurity region) (fig 2b: Cap1 located on F1 and electrically connected to 2a by metal layers and BL1);
a via (¶0040, fig 2B: 201), located in the substrate (¶0021, fig 2B:101) and electrically connected to the second doped region (¶0025, fig 2b: right side 2a second impurity region) (201 is in 101, electrically connected to 2a by active region of 101);
a first dielectric layer (¶0040, insulting later), located between the via (¶0040, fig 2B: 201) and the substrate (¶0021, fig 2B:101) (¶0040 an insulating layer provided between 201, second via 202, and 101); and
a bit line (¶0037, fig 2B: BL2), located on the second surface (¶0021, fig 2B: F2) and electrically connected to the via (¶0040, fig 2B: 201) (¶0040, fig 2b: BL2 located on F2 and electrically connected to 201 by the connection conductive pattern 220).
Regarding claim 2, Roh teaches the dynamic random access memory structure according to claim 1, wherein the word line structure (¶0023, fig 2B: WL/107) is located on the first surface (¶0021, fig 2B: F1) of the substrate (¶0021, fig 2B:101) (¶0028, WL is located on F1 of 101).
Regarding claim 3, Roh teaches the dynamic random access memory structure according to claim 1, wherein the word line structure (¶0023, fig 2B: WL/107)is located in the substrate (¶0021, fig 2B:101)(¶0041, fig 2b: WL located on 101).
Regarding claim 4, Roh teaches the dynamic random access memory structure according to claim 3, further comprising:
a hard mask layer (¶0050, fig 2b: 102 isolation pattern), located in the substrate (¶0021, fig 2B:101) and located on the word line structure (¶0023, fig 2B: WL/107)(fig 2B:102 located in 101 and on WL), wherein the hard mask layer (¶0050, fig 2b: 102 isolation pattern), is closer to the first surface (¶0021, fig 2B: F1) than the word line structure (¶0023, fig 2B: WL/107)(see annotated fig 2b: 102 is closer to F1 than WL).
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Regarding claim 5, Roh teaches the dynamic random access memory structure according to claim 1, wherein the word line structure (¶0023, fig 2B: WL/107) comprises:
a word line (¶0023, fig 2b: WL); and
a second dielectric layer (¶0048, fig 2b: 107 gate dielectric), located between the word line and the substrate (¶0021, fig 2B:101) (WL/107 comprises WL and 107, 107 is located between WL and 101).
Regarding claim 6, Roh teaches the dynamic random access memory structure according to claim 1, wherein the first doped region (¶0025, fig 2b: 2a first impurity region) and the second doped region (¶0025, fig 2b: right side 2a second impurity region) are located in the substrate (¶0021, fig 2B:101) on two sides of the word line structure (¶0023, fig 2B: WL/107) (fig 2b: 2a and right side 2a are in 101 on located on opposite sides of WL/107).
Regarding claim 7, Roh teaches the dynamic random access memory structure according to claim 1, wherein the first doped region (¶0025, fig 2b: 2a first impurity region) and the second doped region (¶0025, fig 2b: right side 2a second impurity region) are located in the substrate (¶0021, fig 2B:101) on a same side of the word line structure (¶0023, fig 2B: WL) (2a and the right side of 2a is located by F1 along with the WL).
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Regarding claim 9, Roh teaches the dynamic random access memory structure according to claim 1, further comprising:
an interconnect structure (¶0043, fig 2a: bit line BL1 and contact plugs BC), located between the capacitor structure (¶0036, fig 2a: Cap1) and the first doped region (¶0025, fig 2a: 2a first impurity region) (fig 2a: BL1 located between Cap1 and 2a) and electrically connected to the capacitor structure (¶0036, fig 2a: Cap1) and the first doped region (¶0025, fig 2a: 2a first impurity region)(¶0030, fig 2a: Cap1 is electrically connected to BL1, and BL1 is electrically connected to 2a).
Regarding claim 10, Roh teaches the dynamic random access memory structure according to claim 1, wherein the capacitor structure (¶0036, fig 2b: Cap1) contacts the first doped region (¶0025, fig 2b: 2a first impurity region). Roh does not explicitly teach wherein the capacitor structure (¶0036, fig 2b: Cap1) directly contacts the first doped region (¶0025, fig 2b: 2a first impurity region). However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the capacitor can directly contact the doped region to optimize capacitance and improve device performance.
Regarding claim 11, Roh teaches the dynamic random access memory structure according to claim 1, wherein the capacitor structure (¶0036, fig 2a: Cap1) comprises:
a first electrode (¶0036, fig 2a: BE1) , electrically connected to the first doped region (¶0025, fig 2a: 2a first impurity region) (fig 2a: Cap1 comprises BE1 electrically connected to 2a);
a second electrode (¶0036, fig 2a: TE1) located on the first electrode (¶0036, fig 2a: BE1); and the second dielectric layer (¶0034, fig 2a: DL1), located between the first electrode (¶0036, fig 2a: BE1) and
the second electrode (¶0036, fig 2a: TE1) (¶0034, fig 2a: DL1 located between BE1 and TE1).
Regarding claim 12, Roh teaches the dynamic random access memory structure according to claim 11, further comprising:
an interconnect structure (¶0043, fig 2a: BL1/BC), located between the first electrode (¶0036, fig 2a: BE1) and the first doped region (¶0025, fig 2a: 2a first impurity region) and electrically connected to the first electrode (¶0036, fig 2a: BE1) and the first doped region (¶0025, fig 2a: 2a first impurity region) (¶0033-¶0034), fig 2a: BL1/BC between BE1 and 2a and electrically connected to BE1).
Regarding claim 13, Roh teaches the dynamic random access memory structure according to claim 11, wherein the first electrode (¶0036, fig 2a: BE1) directly contacts the first doped region (¶0025, fig 2b: 2a first impurity region).
Roh does not explicitly teach wherein the first electrode (¶0036, fig 2a: BE1) directly contacts the first doped region (¶0025, fig 2b: 2a first impurity region). However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the first electrode of the capacitor can directly contact the doped region to optimize capacitance and improve device performance.
Regarding claim 14, Roh teaches the dynamic random access memory structure according to claim 11, wherein a cross-sectional shape of the first electrode (¶0036, fig 2a: BE1) comprises a U-shape (fig 2a).
Regarding claim 15, Roh teaches the dynamic random access memory structure according to claim 11, wherein a cross-sectional shape of the first electrode (¶0036, fig 2a: BE1) comprises a cylindrical shape (fig 2b: elongated rectangle shape).
Regarding claim 16, Roh teaches the dynamic random access memory structure according to claim 1, wherein the via (¶0040, fig 2B: 201) penetrates the second doped region (¶0025, fig 2b: right side 2a second impurity region) (fig 2b: 201 penetrates right side 2a).
Regarding claim 17, Roh teaches the dynamic random access memory structure according to claim 1, wherein the via (¶0040, fig 2B: 201) does penetrate the second doped region (¶0025, fig 2b: right side 2a second impurity region).
Roh does not explicitly teach the via does not penetrate the second doped region. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that to configure the device to not have a via go through the second doped region, to decrease current leakage and optimize device performance.
Regarding claim 18, Roh teaches the dynamic random access memory structure according to claim 1, wherein the via (¶0040, fig 2B: 201) comprises a through-substrate (¶0021, fig 2B: 101) via (¶0040, fig 2B: 201) (fig 2B: 201 goes through 101).
Regarding claim 19, Roh teaches the dynamic random access memory structure according to claim 1, further comprising: a second dielectric layer (¶0037, fig 2b: buffer insulating pattern 205), located between the bit line (fig 2b: BL2) and the second surface (¶0021, fig 2B: F2) (fig 2b: 205 located between BL2 and F2).
Regarding claim 20, Roh teaches the dynamic random access memory structure according to claim 19, wherein the via (¶0040, fig 2B: 201) penetrates the second dielectric layer (¶0037, fig 2b: 205) (fig 2b: 302 penetrates 205).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Roh as applied to claim 7 above, and further in view of Yu (CN 110265397 A).
Regarding claim 8, Roh teaches, the dynamic random access memory structure according to claim 7, wherein there is a first doped region (¶0025, fig 2b: 2a first impurity region) and the second doped region (¶0025, fig 2b: right side 2a second impurity region). Roh fails to teach the first doped region is closer to the first surface than the second doped region. YU teaches a first doped region (page 8 ¶0008 fig 17: 220) is closer to the first surface (page 8 ¶0008, fig 17: top of substrate 202) than the second doped region (page 8 ¶0008, fig 17: 240).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to rearrange the two doped regions of Roh with the configuration of Yu to further reduce the area for forming the transistor, to improve storage function and the integration degree of the device (Yu page 8 ¶0008).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LYTESHIA M PRICE whose telephone number is (571)270-0132. The examiner can normally be reached 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LYTESHIA M PRICE/Examiner, Art Unit 2818
/Jami Valentine Miller/Primary Examiner, Art Unit 2818
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