DETAILED ACTION
Examiner’s Note
The examiner has cited particular passages including column and line numbers, paragraphs as designated numerically and/or figures as designated numerically in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claims, other passages, paragraphs and figures of any and all cited prior art references may apply as well. It is respectfully requested from the applicant, in preparing an eventual response, to fully consider the context of the passages, paragraphs and figures as taught by the prior art and/or cited by the examiner while including in such consideration the cited prior art references in their entirety as potentially teaching all or part of the claimed invention. MPEP 2141.02 VI: “PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS." MPEP 2123 (I): “PATENTS ARE RELEVANT AS PRIOR ART FOR ALL THEY CONTAIN.”
Additionally, in an effort to provide a timely Office response to amendments the Applicant may file in response to this Office Action, it is respectfully requested that, on accompanying remarks/arguments papers, every effort be made to provide specific (page No., paragraph No., FIG. No., etc.) Specification/Drawings support for such amendments, particularly claim amendments.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claim(s) 2-3, 6, 13, 18 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the pertinent prior art of record does not teach or suggest the whole of the claimed limitations, in complete combination with the base claim and any and all intervening claim limitations: wherein the power supply circuit is configured to: generate a first internal driving voltage; and set the first internal voltage interconnection to a high impedance state when the voltage level of the first driving voltage package ball is equal to or higher than a level of the first internal driving voltage or when the voltage level of the first driving voltage package ball is equal to or higher than a reference level; while in regard to claim 3, the pertinent prior art of record does not teach or suggest the whole of the claimed limitations, in complete combination with the base claim and any and all intervening claim limitations: wherein, the first internal voltage interconnection is a high impedance state, when a first external driving voltage is supplied to the at least one memory through the first external voltage interconnection; while in regard to claim 6, the pertinent prior art of record does not teach or suggest the whole of the claimed limitations, in complete combination with the base claim and any and all intervening claim limitations: wherein the power supply circuit is electrically connected to a second driving voltage package ball among the plurality of package balls through a second external voltage interconnection, and is configured to generate, based on a second external driving voltage received through the second external voltage interconnection, a first internal driving voltage to be supplied to the first internal voltage interconnection; while in regard to claim 13, the pertinent prior art of record does not teach or suggest the whole of the claimed limitations, in complete combination with the base claim and any and all intervening claim limitations: wherein a voltage outputted through the first internal voltage interconnection is fed back to the power supply circuit through the first external voltage interconnection; while in regard to claim 18, the pertinent prior art of record does not teach or suggest the whole of the claimed limitations, in complete combination with the base claim and any and all intervening claim limitations: wherein: a first internal driving voltage is supplied through the first internal voltage interconnection; and the first internal driving voltage is fed back to the power supply circuit through the first external voltage interconnection, and wherein, when a voltage level fed back to the power supply circuit through the first external voltage interconnection is equal to or lower than a level of the first internal driving voltage, the power supply circuit is configured to maintain output of the first internal driving voltage.
Claim(s) 7-8 and 19 depend from claim(s) 6 and 18, and as such are therefore also objected for the same reasons.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 14 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. There does not seem to be antecedent for “wherein the power supply is configured to.”
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4-5, 9-12, 15-17 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over CN 115116499 A to Sanuki et al. (“Sanuki”) in view of U.S. Patent/Publication No. 20240055030 to Cheon et al. (“Cheon”).
As to claim 1, Sanuki teaches substantially the claimed invention, including: A semiconductor device (As found in at least FIG. 1: 11) comprising: a package substrate including a plurality of package balls (As found in at least FIG. 1: package 15 including at least pins P1 and P2); at least one memory electrically connected to a first driving voltage package ball among the plurality of package balls through a first external voltage interconnection (As found in at least FIG. 1: memory 12 connected to pin P1 through an external voltage interconnect 13); and a power supply circuit electrically connected to the first driving voltage package ball through the first external voltage interconnection (As found in at least FIG. 1: power supply circuit 14 connected to pin P1 through interconnection 13), electrically connected to the at least one memory through a first internal voltage interconnection (As found in at least FIG. 1: 14 is connected to memory 12 through an internal voltage interconnect: wiring labeled Vbst), and configured to adjust a voltage state of the first internal voltage interconnection based on a voltage level of the first driving voltage package ball (As found in at least FIGS. 1-3, internal voltage labeled Vbst is based on a voltage Vin on pin P1; in the limit, if Vin is 0 volts, Vbst tracks that voltage).
While Sanuki may not expressly mention package balls, Sanuki does teach package pins, such as P1 and p2.
Relevantly and complementarily, Cheon teaches a semiconductor device comprising package balls (As found in at least [0061] and at least FIG. 5C; said packaging including at least memory).
Sanuki and Cheon are analogous art because they are from the same field of endeavor, and/or are reasonably pertinent to the inventor’s problem to be solved: semiconductor devices that may include packaged memory, where the package may include any relevant connectivity to external devices such as ball grid array (BGA), pins, wiring, lead, etc.
At the time of invention, it would have been obvious to a person of ordinary skill in the art to complement the teachings of Sanuki as set forth in this Office action and as found in the reference with the relevant and complementary teachings of Cheon also as set forth in this Office action and as found in the reference(s). The suggestion/motivation would have been obvious to one of ordinary skill in the art before the effective filing date of the present Application: Sanuki’s package pins, such as P1 and P2, can easily be package balls, or package leads or any other type of contact extending from an IC package.
Therefore, it would have been obvious to combine Sanuki with Cheon to make the above modification.
As to claim 4, Sanuki teaches wherein the power supply circuit is configured to: generate a first internal driving voltage; and output the first internal driving voltage to the first internal voltage interconnection when the voltage level of the first driving voltage package ball is lower than a level of the first internal driving voltage or when the voltage level of the first driving voltage package ball is lower than a reference level (As found in at least under “Embodiment 1:” “The memory chip 12 has a terminal TL1 of a boost voltage Vbst boosted by the supply voltage booster circuit 14 and a terminal (second terminal) TL2 connected to a pin (second pin) P2 of the package 15. The voltage level of the signal transmitted and received between the terminal TL2 and the second pin P2 is assumed to be lower than the voltage level of the boosting voltage Vbst;” That is, internal voltage Vbst is a boosted voltage of the external Vin voltage).
As to claim 5, see rejection to at least claim 4: internal voltage Vbst is a boosted voltage of the external Vin voltage.
As to claim 9, Sanuki teaches wherein the power supply circuit is configured to set the first internal voltage interconnection to a high impedance state for a preset time when externally receiving a power-on signal or an operation enable signal (As found in at least FIGS. 1-4: internal voltage Vbst interconnect is at high impedance when transistor 21 is operated at state low at its gate; claim 1, from which this claim depends, requires only: “memory electrically connected to a first driving voltage package ball;” there is no requirement that of an actual voltage on the driving voltage package ball).
As to claim 10, Sanuki teaches wherein the first external voltage interconnection is electrically connected to the first internal voltage interconnection (As found in at least FIG. 4: external interconnection 13 is electrically connected to internal voltage interconnect Vbst).
As to claim 11, Sanuki teaches wherein the first external voltage interconnection is connected to the at least one memory through the first internal voltage interconnection (As found in at least FIGS. 1, 6: external voltage interconnection 13 is connected to at least one memory 12).
As to claim 12, Sanuki teaches wherein a point where the first external voltage interconnection is connected to the power supply circuit is located between a point where the first external voltage interconnection is connected to the first driving voltage package ball and a point where the first external voltage interconnection is connected to the at least one memory (As found in at least FIG. 1: a point along 13 is between pin P1 and an interconnection to 12).
As to claim(s) 15-16, see rejection to at least claim 1; moreover, Sanuki teaches a power management circuit configured to supply an external driving voltage through a package ball included in the semiconductor package (As found in at least FIG. 1, and under “Embodiment 1:” “The reference voltage Vin is supplied from the outside of the package 15 via the pin P1 of the package 15; thus, it is obvious that the reference circuit that supplies Vin is separated from the package pin P1).
As to claim 17, see rejection to at least claim 9.
As to claim 20, see rejection to at least claim(s) 1 and 15.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO N HIDALGO whose telephone number is (571)270-3306. The examiner can normally be reached M-F 9:00-7:30 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 5712721852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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FERNANDO N. HIDALGO
Primary Examiner
Art Unit 2827
/Fernando Hidalgo/Primary Examiner, Art Unit 2827