DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Status of Claims
Claims 1-18 are pending.
Claims 1-18 are original.
Claims 1-18 are rejected herein.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 4-5, 7 and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang (CN 1567584 A).
Note, citations herein below to the text of Huang refer to the machine translation thereof accompanying the current Office Action.
Regarding claim 1, Huang discloses (see, e.g., FIGS. 1-6):
A preparation method of a chip package structure, wherein the method comprises the following steps:
S1 (see FIG. 2A), providing a wafer (2) and producing conductive structures (21, 202) on the wafer (2) based on chip distribution;
S2 (see FIG. 2B), performing wafer dicing (page 5, “cutting the wafer 2 to form a plurality of single chips 20”) based on the chip distribution to obtain chip monomers (20);
S3 (see FIG. 2C), producing plastic package bodies (22) comprising a plurality of chip monomers (20) based on the chip monomers (20); and
S4 (see FIG. 2G), producing electric connection structures (23, 25) on the plastic package bodies (22).
Regarding claim 2, Huang discloses:
The preparation method of a chip package structure according to claim 1, wherein the conductive structures (21, 202) are first balls (21);
step S1 comprises:
S11 (see FIG. 2A), providing a wafer (2) and mounting first balls (21) on the wafer (2) based on the chip distribution; and
step S3 comprises:
S31 (see FIG. 2C), providing a carrier (26) and fixing the chip monomers (20) onto the carrier (26);
S32 (see FIG. 2C), performing plastic packaging (22) on the first balls (21) to form plastic package layers (22), the top surfaces of the plastic package layers (22) being equal to the top ends of the first balls (21); and
S33 (see FIG. 2E), thinning (page 6, “perform … mechanical grinding … to grind the packaging colloid 22 substantially … flush with the conductive bump 21”) the plastic package layers (22) to make the tops of the first balls (21) have flat exposed ends (210).
Note, when the construction of FIG. 2C is view inverted, the surfaces of elements 22 and 21 adjacent element 26 are “top” surfaces equal in height to one another.
Regarding claim 4, Huang discloses:
The preparation method of a chip package structure according to claim 2, wherein the first balls (21) cover PADs (202) of chips (20) on the wafer (2).
Regarding claim 5, Huang discloses:
The preparation method of a chip package structure according to claim 2, wherein step S4 comprises:
S41 (see FIG. 2G), producing rewiring layers (23), opening ink windows (240) and mounting second balls (25) sequentially on the tops of the plastic package layers (22) to produce the electric connection structures (23, 25); and
S42 (see FIG. 2D), releasing the carrier (26) to obtain a plastic package body (22).
Regarding claim 7, Huang discloses:
The preparation method of a chip package structure according to claim 2, wherein the method further comprises the following step:
S5 (see FIG. 2H), cutting the plastic package body (22) after the electric connection structures (23, 25) are produced to obtain a finished package body.
Regarding claim 18, Huang discloses:
A package structure (FIG. 1), wherein the package structure (FIG. 1) is prepared by the preparation method of a chip package structure according to claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Yap (US 9786515 B1).
Regarding claim 3, Huang discloses:
The preparation method of a chip package structure according to claim 2.
Huang does not explicitly disclose wherein the thinning process is performed to reduce 1/3 to 2/3 of the volume or height of the first balls.
However, in analogous art, Yap discloses a thinning process performed to reduce 1/3 to 2/3 of the height of first balls (310). See, e.g., FIG. 8 and column 5, lines 49-54.
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have performed the thinning process to reduce 1/3 to 2/3 of the height of the first balls (21) of Huang as taught by Yap according to known methods to yield predictable results, for example, to maximize and/or otherwise increase the top conductive surfaces (210) of the first balls (21) of Huang. See, e.g., Yap, column 5, lines 49-54.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Furman (US 20030136814 A1).
Regarding claim 8, Huang discloses:
The preparation method of a chip package structure according to claim 2.
Huang does not explicitly disclose wherein the method further comprises the following step performed between step S3 and step S4:
covering the flat exposed ends of the first balls with nickel metal layers.
However, in analogous art, Furman discloses covering exposed ends of studs (24) with nickel metal layers (BARRIER). See, e.g., FIG. 2.
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have, between steps S3 and S4, covered the flat exposed ends (210) of the first balls (21) of Huang with nickel metal layers as taught by Furman according to known methods to yield predictable results, for example, to provide a suitable electrical connection to the conductive traces (23) while acting as a diffusion barrier between the first balls (21) and conductive traces (23).
Claims 6, 9-13 and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Yu (CN 102856279 A).
Note, citations herein below to the text of Yu refer to the machine translation thereof accompanying the current Office Action.
Regarding claim 6, Huang discloses:
The preparation method of a chip package structure according to claim 2.
Huang does not explicitly disclose, wherein in step S31, the bottom surfaces of the chip monomers are fixed onto the top surface of the carrier based on temporary bonding layers.
However, in analogous art, Yu discloses the bottom surfaces of the chip monomers (40) are fixed onto the top surface of the carrier (42) based on temporary bonding layers (44). See, e.g., FIG. 2.
Note, the chip monomers (40) are ultimately removed from the carrier (42). See paragraph [0044]. Hence, the bonding layers (44) is “temporary.”
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have used temporary bonding layers as taught by Yu to fix the bottom surfaces of the chip monomers (20) onto the top surface of the carrier (26) of Huang according to known methods to yield predictable results, for example, to removably secure the chip monomers to the carrier thereby allowing the top surfaces of a plurality chip monomers to be processed in bulk while the back surfaces thereof are fixedly secured to the top of the carrier and then allow the chip monomers to be readily removed from the carrier.
Regarding claim 9, Huang discloses:
The preparation method of a chip package structure according to claim 1, wherein the conductive structures (21, 202) are structural metal layers (21, 202);
step S1 comprises:
S11' (see FIG. 2A), providing a wafer (2) and arranging structural metal layers (21, 202) on the upper surface of the wafer (2) based on the chip distribution; and
step S3 comprises:
S31' (see FIG. 2C), providing a carrier (26) and fixing the chip monomers (20) face down on the carrier (26); and
S32' (see FIG. 2C), performing plastic packaging (22) on the top surface of the carrier (26) to make the top surfaces of plastic package layers (22) higher than the back sides of the chip monomers (20) to obtain plastic package bodies.
Huang does not explicitly disclose temporary bonding layers as claimed.
However, in analogous art, Yu discloses temporary bonding layers (44) for temporarily fixing chips monomers (40) on a carrier (42). See, e.g., FIG. 2.
Note, the chip monomers (40) are ultimately removed from the carrier (42). See paragraph [0044]. Hence, the bonding layers (44) is “temporary.”
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have used temporary bonding layers as taught by Yu to fix the chip monomers (20) on the carrier (26) of Huang according to known methods to yield predictable results, for example, to removably secure the chip monomers to the carrier thereby allowing a plurality chip monomers to be processed in bulk while fixedly secured to the carrier and then allow the chip monomers to be readily removed from the carrier.
Regarding claim 10, Huang in view of Yu as applied to claim 9 discloses the preparation method of a chip package structure according to claim 9.
Huang does not explicitly disclose wherein the structural metal layers are under bump metallization (UBM) layers.
However, in analogous art, Yu discloses structural metal layers (56, 50) that are under bump metallization (UBM) layers (56). See, e.g., FIG. 19.
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have used structural metal layers (56, 50) that are under bump metallization (UBM) layers (56) as taught by Yu in the device of Huang according to known methods to yield predictable results, for example, to use a readily available and known component and/or technique (i.e., UBM) for its known and intended purpose (i.e., to make an effective electrical connection between the bumps (21) and bonding pads (202) of Huang).
Regarding claim 11, Huang in view of Yu as applied to claim 10 discloses the preparation method of a chip package structure according to claim 10.
Yu further discloses:
wherein when the structural metal layers (56, 50) are the UBM layers (56), the step of arranging the structural metal layers comprises:
S111, defining a passivation pattern (54) on the upper surface of the wafer (200) based on the chip distribution; and
S112, depositing the UBM layers (56) on the upper surface of the wafer (200) according to the passivation pattern (54).
Regarding claim 12, Huang in view of Yu as applied to claim 11 discloses the preparation method of a chip package structure according to claim 11.
Huang does not explicitly disclose:
wherein the step of arranging the structural metal layers comprises the following step performed before step S111:
S110, providing dielectric thickening layers surrounding the PADs on the upper surface of the wafer based on the chip distribution.
However, in analogous art, Yu discloses:
wherein the step of arranging the structural metal layers (56, 50) comprises the following step performed before step S111:
S110, providing dielectric thickening layers (49, 66) surrounding the PADs (28) on the upper surface of the wafer based on the chip distribution.
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have used dielectric thickening layers surrounding the PADs as taught by Yu in the device of Huang according to known methods to yield predictable results, for example, to protect the underlying chips during further processing.
Regarding claim 13, Huang in view of Yu as applied to claim 12 discloses the preparation method of a chip package structure according to claim 12.
Yu further discloses wherein the dielectric thickening layers (49, 66) are polyimide (PI) protective layers with a plurality of enclosing pores to surround the respective PADs (28) on the wafer.
Regarding claim 16, Huang in view of Yu as applied to claim 9 discloses the preparation method of a chip package structure according to claim 9.
Huang further discloses wherein the structural metal layers (21) cover the PADs (202) of the respective chips (20) on the wafer (2). See, e.g., FIG. 2A.
Regarding claim 17, Huang in view of Yu as applied to claim 9 discloses the preparation method of a chip package structure according to claim 9.
Huang further discloses wherein step S4 comprises:
S41', releasing (see FIG. 2D) the carrier (26) from the plastic package bodies (22); and
S42', inverting (compare FIG. 2F to FIG. 2E) the plastic package bodies (22) after the carrier (26) is released, and producing rewiring layers (23), opening ink windows (240) and mounting balls (25) sequentially.
Claims 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Yu as applied to claim 11 above, and further in view of Chen (CN 115692330 A).
Note, citations herein below to the text of Chen refer to the machine translation thereof accompanying the current Office Action.
Regarding claim 14, Huang in view of Yu as applied to claim 11 discloses the preparation method of a chip package structure according to claim 11.
Yu further discloses wherein the UBM layers (56, 50) comprise sinking metal structural bodies (50), the number of the sinking metal structural bodies (50) is the same as that of the PADs (28) on the wafer.
Yu does not explicitly disclose that the sinking bottoms of the sinking metal structural bodies completely cover the corresponding PADs.
However, in analogous art, Chen discloses sinking metal structural bodies (5) for making an electrical connection to corresponding PADs (12), where the sinking metal structural bodies (5) completely cover the corresponding PADs (12). See, e.g., FIG. 15d.
Note, the corresponding PADs of Chen are taken as only that portion of element (12) exposed from element (11).
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have used made the device of Huang in view of Yu such that the sinking bottoms of the sinking metal structural bodies completely cover the corresponding PADs as taught by Chen according to known methods to yield predictable results, for example, to maximize the surface area of electrical connections to the PADs.
Regarding claim 15, Huang in view of Yu and Chen as applied to claim 14 discloses the preparation method of a chip package structure according to claim 14.
Yu further discloses wherein the sinking metal structural bodies (50) sink inwards obliquely. See, e.g., FIG. 19.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN P CORNELY whose telephone number is (571)272-4172. The examiner can normally be reached Monday - Thursday 8:30 AM - 4:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
JOHN P. CORNELY
Examiner
Art Unit 2812
/J.P.C./Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
Prosecution Insights