Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Status of the Claims
Applicant’s election, provisionally of Group I, claims 1-11, in the reply filed on August 26th, 2026, is acknowledged. Because applicants did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.03(a)). Non-elected invention of Group II and III, claims 12-20 have been withdrawn from consideration. Claims 1-20 are pending.
Action on merits of Group I, claims 1-11 as follows.
Priority
Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on June 21st, 2024, has been considered by the examiner.
Drawings
The drawings filed on 06/21/2024 are acceptable.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1-11 are rejected under 35 U.S.C. 103 as being unpatentable over Mao (US 2020/0035618, hereinafter as Mao ‘618) in view of Wang (US 2024/0047365, hereinafter as Wang ‘365) and further in view of Tseng (US 2020/0381362, hereinafter as Tsen ‘362).
Regarding Claim 1, Mao ‘618 teaches a semiconductor package comprising:
a package substrate (Fig. 7, (106); [0018]);
a first semiconductor chip (Fig. 1E, (104A); [0018]) on the package substrate and including a plurality of first through vias (110A; [021]);
a second semiconductor chip (Fig. 1E, (104B); [0018]) spaced apart from the first semiconductor chip (104A) in a lateral direction parallel to an upper surface of the package substrate (106) and including a plurality of second through vias (110B);
a third semiconductor chip (122; [0033]) on the first semiconductor chip;
an interposer (302; [0066]) between the third semiconductor chip (122) and the first semiconductor chip (104A) and electrically connecting the first semiconductor chip (104A) to the third semiconductor chip (122);
a molding layer (134; [0023] and [0059]) on the first semiconductor chip (104A) and the second semiconductor chip (see Figs. 1A and 1G);
a first solder ball (304; [0066]) between the first semiconductor chip (104A) and the interposer (302); and
a second solder ball (304; [0066]) between the second semiconductor chip and the interposer (302), wherein the interposer comprises: a first pattern structure (302_left) that electrically connects the first semiconductor chip (104A) to the third semiconductor chip (122); a second pattern structure (302_right) that electrically connects the second semiconductor chip (104B) to the third semiconductor chip (122).
Thus, Mao ‘618 is shown to teach all the features of the claim with the exception of explicitly the features: “a third pattern structure that electrically connects the first semiconductor chip to the second semiconductor chip”.
However, Wang ‘365 teaches a third pattern structure (Fig. 2H, (208b); [0061]) that electrically connects the first semiconductor chip (102D; [0040]) to the second semiconductor chip (102C; [0040]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Mao ‘618 by having a third pattern structure that electrically connects the first semiconductor chip to the second semiconductor chip for the purpose of providing electrical connection between the chip structures in order to improve the performance and reliability of the package structure as suggested by Wang ‘365.
Thus, Mao ‘618 and Wang ‘365 are shown to teach all the features of the claim with the exception of explicitly the features: “a molding layer between the package substrate and the interposer”.
Tsen ‘362 teaches a molding layer (Fig. 5, (112); [0013]) between the package substrate (152; [0024]) and the interposer (120; [0017]). Examiner considers the heat dissipation member (152) is the package substrate.
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Mao ‘618 and Wang ‘365 by having a molding layer between the package substrate and the interposer for increasing performance and lower power consumption (see para. [0008]) as suggested by Tsen ‘362.
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Fig. 7 (Mao ‘618)
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Fig. 1H (Wang ‘365)
Regarding Claim 2, Mao ‘618 teaches the first pattern structure (302_left; [0066]) overlaps the first semiconductor chip (104A) in a vertical direction perpendicular to the upper surface of the package substrate and does not overlap the second semiconductor chip in the vertical direction, wherein the second pattern structure (302_right; [0066]) overlaps the second semiconductor chip (104B) in the vertical direction and does not overlap the first semiconductor chip in the vertical direction.
Wang ‘365 teaches the third pattern structure (208b; [0061]) overlaps a portion of the first semiconductor chip (102D) and a portion of the second semiconductor chip (102C) in the vertical direction (see Fig. 2H).
Regarding Claim 3, Mao ‘618 teaches an upper surface of the first semiconductor chip (104A) comprises: a first connection region (304) that overlaps the plurality of first through vias (110A) in a vertical direction perpendicular to the upper surface of the package substrate; and a first non-connection region that is a region other than the first connection region, and wherein the first non-connection region is wider than the first connection region in the lateral direction (see Fig. 7).
Regarding Claim 4, Mao ‘618, Wang ‘365 and Tsen ‘362 are shown to teach all the features of the claim with the exception of explicitly the features: “the first connection region is closer to the second semiconductor chip than the first non-connection region”.
However, it has been held to be within the general skill of a worker in the art to select the first connection region is closer to the second semiconductor chip than the first non-connection region on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
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A person of ordinary skills in the art is motivated to select the first connection region is closer to the second semiconductor chip than the first non-connection region in order to improve the connectivity of the semiconductor package.
Regarding Claim 5, Mao ‘618 teaches the first non-connection region is covered by the molding layer (134) (see Fig. 7).
Regarding Claim 6, Mao ‘618 teaches an upper surface of the second semiconductor chip (104B) comprises: a second connection region (304) that overlaps the plurality of second through vias (110B) in a vertical direction perpendicular to the upper surface of the package substrate; and a second non-connection region that is a region other than the second connection region, and wherein the second non-connection region is wider than the second connection region in the lateral direction (see Fig. 7).
Regarding Claim 7, Tsen ‘362 teaches the first solder ball (1161; [0016]) is one of a plurality of first solder balls between the first semiconductor chip (114; [0011]) and the interposer (120; [0017]) (see Fig. 3), wherein the second solder ball is one of a plurality of second solder balls between the second semiconductor chip and the interposer (see Fig. 3), wherein the interposer further comprises: a plurality of first connection pads (1162; [0016]) on a lower surface of the interposer (120) and in contact with the plurality of first solder balls (1161), respectively, and the plurality of second solder balls, respectively; and a plurality of second connection pads (126; [0017]) on an upper surface of the interposer (120); a first via extending from the first wiring pattern and electrically connected to a first one of the plurality of first connection pads (1162) (see Fig. 5); and a second via extending from the first wiring pattern and electrically connected to a first one of the plurality of second connection pads, and wherein the first via overlaps a first one of the plurality of first solder balls (1161) in a vertical direction perpendicular to the upper surface of the package substrate (152) (see Fig. 5).
Wang ‘365 teaches the first pattern structure comprises: a first wiring pattern (108b; [0024]) extending in the lateral direction.
Regarding Claim 8, Wang ‘365 teaches the second pattern structure comprises: a second wiring pattern (108b; [0024]) extending in the lateral direction.
Tsen ‘362 teaches a third via extending from the second wiring pattern and electrically connected to a second one of the plurality of first connection pads (1162); and a fourth via extending from the second wiring pattern and electrically connected to a second one of the plurality of second connection pads (126), and wherein the third via overlaps a first one of the plurality of second solder balls (1161) in the vertical direction (see Fig. 5).
Regarding Claim 9, Wang ‘365 teaches the third pattern structure (208b) comprises: a third wiring pattern extending in the lateral direction (see Fig. 2H);
Tsen ‘362 teaches a fifth via extending from the third wiring pattern and electrically connected to a second one of the plurality of first connection pads (1162); and a sixth via extending from the third wiring pattern and electrically connected to a third one of the plurality of first connection pads (1162), and wherein the fifth via overlaps a second one of the plurality of first solder balls (1161) in the vertical direction, and the sixth via overlaps a first one of the plurality of second solder balls in the vertical direction (see Fig. 5).
Regarding Claim 10, Mao ‘618, Wang ‘365 and Tsen ‘362 are shown to teach all the features of the claim with the exception of explicitly the features: “a lower portion of the first solder ball has a width in the lateral direction that decreases toward an upper surface of the first semiconductor chip, wherein a lower portion of the second solder ball has a width in the lateral direction that decreases toward an upper surface of the second semiconductor chip, and wherein an upper portion of each of the first solder ball and the second solder ball has a width in the lateral direction that decreases toward the interposer”.
However, it has been held to be within the general skill of a worker in the art to select a lower portion of the first solder ball has a width in the lateral direction that decreases toward an upper surface of the first semiconductor chip, wherein a lower portion of the second solder ball has a width in the lateral direction that decreases toward an upper surface of the second semiconductor chip, and wherein an upper portion of each of the first solder ball and the second solder ball has a width in the lateral direction that decreases toward the interposer on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
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A person of ordinary skills in the art is motivated to select a lower portion of the first solder ball has a width in the lateral direction that decreases toward an upper surface of the first semiconductor chip, wherein a lower portion of the second solder ball has a width in the lateral direction that decreases toward an upper surface of the second semiconductor chip, and wherein an upper portion of each of the first solder ball and the second solder ball has a width in the lateral direction that decreases toward the interposer in order to improve the performance of the semiconductor package.
Regarding Claim 11, Wang ‘365 teaches each of the first semiconductor chip and the second semiconductor chip comprises a logic chip, and wherein the third semiconductor chip comprises a memory chip (see para. [0025] and [0043]).
Examiner’s Note
Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraph numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following patents are cited to further show the state of the art with respect to semiconductor devices:
Pasdast et al. (US 2023/0245999 A1)
Brun et al. (US 2023/0074181 A1)
Lin et al. (US 2021/0111153 A1)
Chen et al. (US 2017/0125379 A1)
Jiang et al. (US 2003/0230801)
For applicant’s benefit portions of the cited reference(s) have been cited to aid in the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DZUNG T TRAN whose telephone number is (571) 270-3911. The examiner can normally be reached on M-F 8 AM-5PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DZUNG TRAN/
Primary Examiner, Art Unit 2893
