Prosecution Insights
Last updated: July 17, 2026
Application No. 18/749,794

LIGHT-EMITTING SUBSTRATE, METHOD OF MANUFACTURING LIGHT-EMITTING SUBSTRATE, AND DISPLAY DEVICE

Non-Final OA §102
Filed
Jun 21, 2024
Priority
May 11, 2020 — CN 202010395225.7 +2 more
Examiner
ULLAH, ELIAS
Art Unit
Tech Center
Assignee
BOE Technology Group Co., Ltd.
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
3m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
721 granted / 850 resolved
+24.8% vs TC avg
Moderate +8% lift
Without
With
+7.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
21 currently pending
Career history
859
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
48.0%
+8.0% vs TC avg
§102
48.2%
+8.2% vs TC avg
§112
1.3%
-38.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 850 resolved cases

Office Action

§102
DETAILED ACTION Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-2 and 13-15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lee et al. (Lee, US 2022/0310579 A1) IDS of the record. Regarding claims 1 and 13, Lee shows a light-emitting substrate (substrate 101 in FIG. 2), comprising: a first substrate (substrate 101), wherein the first substrate comprises: a first base substrate (AS in FIG. 2); a light-emitting diode (LE in FIG. 2) arranged on the first base substrate (AS in FIG. 2); and a first conductive pad (PAD 2) arranged on the first base substrate; a second substrate (substrate 101) arranged opposite to the first substrate, wherein the second substrate comprises: a second base substrate (substrate 101); and a second conductive pad (PAD 1) arranged on the second base substrate; and a bonding wire ( wire CE) structure comprising a bonding wire, wherein the first conductive pad is located on a surface of the first substrate away from the second substrate (see FIG. 2), the second conductive pad is located on a surface of the second substrate away from the first substrate (see FIG. 2), and the bonding wire is configured to electrically connect the first conductive pad and the second conductive pad (see FIG. 2); wherein the bonding wire structure further comprises a first solder joint (PD as shown in FIG 3) and a second solder joint, an end of the bonding wire is soldered to the first conductive pad at the first solder joint (PD), and another end of the bonding wire is soldered to the second conductive pad at the second solder joint; and wherein the bonding wire comprises, at each of the first solder joint and the second solder joint, a portion that has an angle with a plane in which the first base substrate is located and/or that has a curved arc (see FIG. 2). Regarding claim 2, Lee shows a light-emitting substrate (substrate 101 in FIG. 2), comprising: a first substrate (substrate 101), further comprising a gum (CP in FIG. 2), wherein the gum is arranged between the first substrate and the second substrate and configured to attach the first substrate and the second substrate together (see FIG. 2). Regarding claim 14, Lee shows a method of manufacturing a light-emitting substrate, comprising: providing a first substrate (substrate 101 in FIG. 2), wherein the first substrate comprises a first base substrate (AS in FIG. 2) and a first conductive pad (PAD 2) provided on the first base substrate (AS); transferring and bonding a light-emitting diode (LE) to the first substrate; providing a second substrate (substrate 101), wherein the second substrate (substrate 101) comprises a second base substrate and a second conductive pad (PAD 2) provided on the second based substrate; placing the first substrate and the second substrate on a carrier so as to maintain a relative position of the first substrate and the second substrate (see FIG. 2-3); forming a bonding wire structure to electrically connect the first conductive pad and the second conductive pad; and turning the second substrate toward the first substrate, so that a surface of the second base substrate away from the second conductive pad faces the first substrate, that the first conductive pad is located on a surface of the first substrate away from the second substrate, and that the second conductive pad is located on a surface of the second substrate away from the first substrate, wherein the bonding wire (CE in FIG. 2) structure comprises a bonding wire configured to electrically connect the first conductive pad and the second conductive pad; wherein an end of the bonding wire is soldered to the first conductive pad at a first solder joint (PD in FIG. 3), and another end of the bonding wire is soldered to the second conductive pad at a second solder joint; and wherein the bonding wire comprises, at each of the first solder joint and the second solder joint, a portion that has an angle with a plane in which the first base substrate is located and/or that has a curved arc (see FIG. 2-3). Regarding claim 15, Lee shows a method of manufacturing a light-emitting substrate, comprising: providing a first substrate (substrate 101 in FIG. 2), wherein after placing the first substrate and the second substrate on the carrier and before forming the bonding wire structure, the method further comprises: forming a first protective adhesive layer, so that the first protective adhesive layer covers at least a first sidewall of the first substrate adjacent to the first conductive pad and a second sidewall of the second substrate adjacent to the second conductive pad (see FIG. 2-3). Allowable Subject Matter Claims 3-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIAS M ULLAH whose telephone number is (571)272-1415. The examiner can normally be reached M-F at 8AM-5PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara Green can be reached at 571-270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ELIAS ULLAH/Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Jun 21, 2024
Application Filed
Jul 01, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12667017
LIGHT EMITTING DEVICE MODULE AND DISPLAY APPARATUS HAVING THE SAME
2y 11m to grant Granted Jun 23, 2026
Patent 12666630
SEMICONDUCTOR DEVICE
2y 10m to grant Granted Jun 23, 2026
Patent 12667025
SEMICONDUCTOR MEMORY DEVICE
2y 1m to grant Granted Jun 23, 2026
Patent 12660722
POWER MODULE PACKAGE WITH MOLDED VIA AND DUAL SIDE PRESS-FIT PIN
3y 7m to grant Granted Jun 16, 2026
Patent 12660208
STORAGE WAFER AND MANUFACTURING METHOD OF STORAGE WAFER
3y 3m to grant Granted Jun 16, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
93%
With Interview (+7.8%)
2y 4m (~3m remaining)
Median Time to Grant
Low
PTA Risk
Based on 850 resolved cases by this examiner. Grant probability derived from career allowance rate.

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