DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 11 – 14 and 20 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Tran et al. (US Pat Pub 2005/0024956).
Regarding claims 1, 14 and 20, Tran et al. disclose an apparatus (figs. 1 – 26 and all related texts) comprising:
a memory array (see abstract: “regular memory arrays and redundant memory arrays”); and
a NOR decoder for accessing the memory array (for example fig. 11 or 12), the NOR decoder comprising:
a first NOR decode circuit (for example the NOR circuit 1101) connected by a first node to an evaluation circuit (1101 connected to first input of NAND gate evaluation circuit 1103, fig. 11), the first NOR decode circuit being configured to receive a first set of three or more inputs (referred to as inputs 712-0 – 712-3), wherein the evaluation circuit is connected to a second node (referred to as the output of circuit 1103); and
a second NOR decode circuit (1102) connected by a third node to the evaluation circuit (output of NOR circuit 1102 connected to second input node of NAND circuit 1103), the second NOR decode circuit (1102) being configured to receive a second set of three or more inputs (referred to as inputs 712-4 – 712-7, fig. 11), wherein the evaluation circuit is configured to change a state of the second node in response to an active clock signal (see para 0080, 0082, 0085, 0088 and 0097, etc…, which synchronizes the operations of the memory system) and all inputs in the first set and the second set having a same logical value (inherent as 1101 and 1102 are NOR gate circuits and 1103 is an NAND gate circuit. This means the output of 1103 assert when all inputs of 1101 and 1102 have same logical value).
Regarding claims 11, Tran et al. also disclose the NOR decoder of claim 1, wherein the second node (output of NAND circuit 1103, fig. 11) is pulled from high to low in response to all inputs in the first set and the second set being low (inherent given the nature of NOR AND NAND digital circuits operation).
Regarding claim 12, Tran et al. also disclose the NOR decoder of claim 1, further comprising an inverter coupled between the second node and an output node (referred to as the NOT output which makes up the NAND function of the output of NAND circuit 1103, fig. 11).
Regarding claim 13, Tran et al. also disclose the NOR decoder of claim 1, wherein the NOR decoder is a complimentary NOR-NAND decoder (gate 1101/1102 being NOR circuit and gate 1103 being NAND circuit, fig. 11).
Allowable Subject Matter
Claims 2 – 10 and 16 – 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior arts of record fail to teach or reasonably suggest the NOR decoder as set forth above, further comprising, in combination, the features and limitations additionally claimed at least in claims 2, 3, 5, 7 – 10 (with respect to claim 1), and 15, 16, and 18 (with respect to claim 14).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
See additional cited references for related disclosures to the claimed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LY D PHAM whose telephone number is (571)272-1793. The examiner can normally be reached M-F: 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 571-272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
LY D. PHAM
Examiner
Art Unit 2827
/LY D PHAM/
Primary Examiner, Art Unit 2827 February 2, 2026