DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/21/2024 is being considered by the examiner.
Drawings
The drawings submitted on 06/21/2024 are being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 2 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Chu et al. (US 20230307449 A1).
Regarding claim 1, Chu discloses a semiconductor integrated circuit (IC) device comprising:
a first region (103b) comprising a first fin (406b3) upon a backside interlayer dielectric (ILD) (116), the first fin (106b3) having a first fin height (Hu1); ([0006], Fig. 4B) and
a second region (103c) comprising a second fin (406c) upon the backside ILD (116), the second fin (406c) having a second fin height that is less than the first fin height. ([0087], Fig. 4B)
Regarding claim 2, Chu discloses the semiconductor IC device of claim 1, wherein a top surface of the first fin (406b3) is coplanar with a top surface of the second fin (406c). (Fig. 4B)
Claims 18 is rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Cheng et al. (US 20180122706 A1).
Regarding claim 18, Cheng discloses a semiconductor integrated circuit (IC) device fabrication method comprising: forming a pair of fins (131) within a substrate structure (110); ([0057], Fig. 3-4)
forming a fin plug (175) between the pair of fins (131); ([0087], Fig. 7-8)
after forming the fin plug (175), forming shallow trench isolation (STI) openings (190) within the substrate structure (110) below and adjacent to the pair of fins (131); ([0097], Fig. 12) and
forming a respective STI region (195) within the STI openings (190). ([0195], Fig. 19)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Chu et al. (US 20230307449 A1).
Regarding claim 3, Chu discloses the semiconductor IC device of claim 2., and wherein the first region (103b) further comprises a first FinFET comprising first source/drain (S/D) regions (120/122) and the first fin (106b3). ([0067], Fig. 1B shows the source and drain configurations which can be applied to each Fin and any embodiment of the disclosure)
Chu does not explicitly disclose wherein first shallow trench isolation (STI) regions at least partially bound the first region
However, Chu discloses:
“[0062] As illustrated in FIG. 1A, the lower regions 107 of the various fins extend within the ILD 116. In an example, the ILD 116 acts as shallow trench isolation (STI), to electrically isolate the lower regions of the various adjacent fins. In some embodiments, ILD 116 (which may also be referred to as an STI layer) may include any suitable electrically insulating material, such as an oxide (e.g., silicon dioxide) or nitride (e.g., silicon nitride) or carbide (e.g., silicon carbide)”
Therefore, it would have been obvious to one skilled in the art before the effective filing date to use the teachings of Chu to have first shallow trench isolation (STI) regions at least partially bound the first region in order to “electrically isolate the lower regions of the various adjacent fins.” (Chu, [0062])
Regarding claim 4, Chu discloses the semiconductor IC device of claim 3 wherein the second region (103c) further comprises a second FinFET comprising second source/drain (S/D) regions (120/122) and the second fin (406c). ([0067], Fig. 1B shows the source and drain configurations which can be applied to each Fin and any embodiment of the disclosure)
Chu does not explicitly disclose wherein second STI regions at least partially bound the second region.
However, Chu discloses:
“[0062] As illustrated in FIG. 1A, the lower regions 107 of the various fins extend within the ILD 116. In an example, the ILD 116 acts as shallow trench isolation (STI), to electrically isolate the lower regions of the various adjacent fins. In some embodiments, ILD 116 (which may also be referred to as an STI layer) may include any suitable electrically insulating material, such as an oxide (e.g., silicon dioxide) or nitride (e.g., silicon nitride) or carbide (e.g., silicon carbide)”
Therefore, it would have been obvious to one skilled in the art before the effective filing date to use the teachings of Chu to have second STI regions at least partially bound the second region in order to “electrically isolate the lower regions of the various adjacent fins.” (Chu, [0062])
Claims 5-10 are rejected under 35 U.S.C. 103 as being unpatentable over Chu et al. (US 20230307449 A1) as applied to claim 4 above, and further in view of Cheng et al. (US 9385023 B1).
Regarding claim 5, Chu discloses the semiconductor IC device of claim 4. Chu does not disclose wherein a bottom surface of the first fin is substantially coplanar with a top surface of the first STI regions.
However, Cheng discloses:
wherein a bottom surface of the first fin (34B) is substantially coplanar with a top surface of the first STI regions (32). (col. 11 lines, 33-35, Fig. 11-12)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Chu and Cheng for a bottom surface of the first fin is substantially coplanar with a top surface of the first STI regions as an obvious matter of design choice, In re Rose, 105 USPQ 237 (CCPA 1955). See MPEP 2144.04, so as to “improve performance in addition to scaling”. (Cheng, col. 1, line 14-26)
Regarding claim 6, Cheng discloses the semiconductor IC device of claim 5, wherein a bottom surface of the second fin (34A) is above a top surface of the second STI regions (32). (Fig. 11-12)
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Cheng for similar reasons mentioned beforehand.
Regarding claim 7, Cheng discloses the semiconductor IC device of claim 6, wherein the top surface of the first STI regions (32) and the top surface of the second STI regions (32) are substantially coplanar. (Fig. 11-12)
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Cheng for similar reasons mentioned beforehand.
Regarding claim 8, Cheng discloses the semiconductor IC device of claim 7, wherein the first FinFET further comprises a first gate (44B) and wherein a bottom surface of the first gate is substantially coplanar with the bottom surface of the first fin (34B). (col. 14, lines 1-5, Fig. 12)
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Cheng for similar reasons mentioned beforehand.
Regarding claim 9, Cheng discloses the semiconductor IC device of claim 8, wherein the second FinFET further comprises a second gate (44A).
Cheng does not explicitly disclose:
wherein a bottom surface of the second gate is substantially coplanar with the top surface of the second STI regions.
However, one ordinarily skilled in the art could use the configuration of the gate in 40B and apply it to the gate of 40A because it would have been an obvious matter of design choice to include a bottom surface of the second gate is substantially coplanar with the top surface of the second STI regions, since such a modification would have involved a mere change in the size of component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). See MPEP 2144.04.
Regarding claim 10, Cheng discloses the semiconductor IC device of claim 9, wherein the backside ILD (30A/30B) comprises a backside ILD portion (30A) between the bottom surface of the second fin (34A) and the top surface of the second STI regions (32). (col. 17, lines 13, Fig. 12)
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Cheng for similar reasons mentioned beforehand.
Claims 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US 9385023 B1) as applied to claim 10 above, and further in view of Lin et al. (US 20220384202 A1).
Regarding claim 11, Cheng discloses the semiconductor IC device of claim 10. Cheng does not disclose further comprising: a frontside back end of line (BEOL) network; and a backside BEOL network.
However, Lin discloses:
a frontside back end of line (BEOL) network (250); ([0071], Fig. 29) and
a backside BEOL network (290). ([0080], Fig. 29)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Cheng and Lin to include a frontside back end of line (BEOL) network; and a backside BEOL network so that “more routing space can be provided for the integrated circuit structure 100.” (Lin, [0081])
Regarding claim 12, Lin discloses the semiconductor IC device of claim 11, wherein the first gate (220) and the second gate (another 220) are respectively electrically connected to the frontside BEOL network (250). ([0064], Fig. 29)
It would have been obvious to use the teachings of Lin for similar reasons mentioned beforehand.
Regarding claim 13, Lin discloses the semiconductor IC device of claim 12, wherein one of the first S/D regions (left side 200) is electrically connected to the frontside BEOL network (250) by a frontside contact (240) and another of the first S/D regions (middle 200) is electrically connected to the backside BEOL network (290) by a backside contact (285). ([0070], [0080], Fig. 29)
It would have been obvious to use the teachings of Lin for similar reasons mentioned beforehand.
Regarding claim 14, Lin discloses the semiconductor IC device of claim 13, wherein the first FinFET further comprises a first gate inner spacer (170) in contact with a sidewall of the first gate (220) and with a sidewall of one of the first S/D regions (200) and a second gate inner spacer (170) in contact with an opposite sidewall of the first gate (220) and with a sidewall of another of the first S/D regions (200). ([0037], Fig. 29)
It would have been obvious to use the teachings of Lin for similar reasons mentioned beforehand.
Claims 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over You et al. (US 20160379982 A1) in view of Chu et al. (US 20230307449 A1).
Regarding claim 15, You discloses a semiconductor integrated circuit (IC) device comprising:
a first FinFET (B1) comprising a first fin (F1) comprising a first effective channel width (WT1); ([0100], Fig. 1B) and
a second FinFET (B2) comprising a second fin (F2) a second effective channel width (WT2) that is less than the first effective channel width (WT1). ([0101], Fig. 1B-7B)
You does not disclose:
a backside interlayer dielectric (ILD)
However, Chu discloses:
a backside interlayer dielectric (ILD), (116), (Fig. 1B-7B)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of You and Chu to have a backside interlayer dielectric (ILD) in order to “electrically isolate the lower regions of the various adjacent fins.” (Chu, [0062])
Regarding claim 16, You discloses the semiconductor IC device of claim 15, wherein a top surface of the first fin (F1) is coplanar with a top surface of the second fin (F2). (Fig. 1B-7B)
Regarding claim 17, You discloses the semiconductor IC device of claim 16, wherein a first fin (F1) thickness is substantially the same as a second fin (F2) thickness. (Fig. 4B)
Claims 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US 20180122706 A1) as applied to claim 18 above, and further in view of Chu et al. (US 20230307449 A1).
Regarding claim 19, Cheng discloses the semiconductor IC device fabrication method of claim 18. Cheng does not disclose further comprising:
from a backside of the semiconductor IC device, removing the substrate structure between the STI regions below the pair of fins.
However, Chu discloses:
from a backside (113) of the semiconductor IC device (100), removing the substrate (302) structure between the STI regions (116 per [0062]) below the pair of fins (106a/b/c). (Fig. 3A-13)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Cheng and Chu to include the step from a backside of the semiconductor IC device, removing the substrate structure between the STI regions below the pair of fins in order to “ to tune the characteristics of the transistor,” for “forming interconnect features for power delivery and/or signal routing within the backside of the integrated circuit.” (Chu, [0029]-[0030])
Regarding claim 20, Chu discloses the semiconductor IC device fabrication method of claim 19, wherein removing the substrate structure (302) between the STI regions (116) below the pair of fins (106a/b/c) further comprises: further removing a respective portion of the pair of fins (106a/b/c) above the STI regions (116). (Fig. 3A-13)
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Chu for similar reasons mentioned beforehand.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ASHLEY BLACKWELL whose telephone number is (703)756-1508. The examiner can normally be reached Mon-Fri 8:00-1600.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ASHLEY NICOLE BLACKWELL/Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
Prosecution Insights