DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-15 and 20-27 in the reply filed on 8/21/2026 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6/21/2024, 1/13/2025 and 2/18/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5-7, 9-10 and 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Bai et al. CN 114335010A and Ban et al. US 2020/0144297.
Re claim 1, Bai teaches a thin film transistor substrate (fig1) comprising:
a light blocking layer (2, fig1, [60]) disposed on a substrate (104, fig1, [67]);
an active layer (4, fig1, [61]) disposed on the light blocking layer (2, fig1, [60]), the active layer (4, fig1, [61]) including a lower hole (18b, fig3C, [57]) in one side of the active layer;
a gate electrode (6 or 8, fig1, [64]) disposed on the active layer;
a source electrode (10a, fig1, [62]) electrically connected to both of the active layer (4, fig1, [61]) and the light blocking layer (2, fig1, [60]); and
an insulating layer (9, 7, 5, fig1, [63]) disposed between the active layer (4, fig1, [61]) and the source electrode (10a, fig1, [62]), the insulating layer including an upper hole (18a, fig1, [57]),
wherein the source electrode (10a, fig1, [62]) includes a lower electrode (part of 10a in 18b, fig1) disposed in the lower hole (18b, fig3C, [57]) in the active layer (4, fig1, [61]) and an upper electrode (part of 10a in 18a, fig1) disposed in the upper hole (18a, fig3C, [57]) in the insulating layer (9, 7, 5, fig1, [63]),
wherein the active layer (4, fig1, [61]) and the light blocking layer (2, fig1, [60]) are electrically connected to each other through the lower electrode (part of 10a in 18b, fig1).
Bai does not explicitly show wherein an area of a lower surface of the upper electrode is larger than an area of an upper surface of the lower electrode.
Ban teaches an area of a lower surface of the upper electrode (281, fig2A, [57]) is larger than an area of an upper surface of the lower electrode (282, fig2A, [57]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Bai and Ban to form the via hole with the process of Ban. The motivation to do so is to reduce process difficulty while increase the contact area between the electrode and the active layer (Ban, [57]).
Re claim 2, Bai modified above teaches the thin film transistor substrate according to claim 1, wherein the upper hole (18a, fig3C, [57]) and the lower hole (18b, fig3C, [57]) are in communication with each other.
Re claim 3, Bai modified above teaches the thin film transistor substrate according to claim 1, wherein the upper electrode (part of 10a in 18a, fig1) contacts an entire upper surface of the lower electrode (part of 10a in 18b, fig1) and a portion of an upper surface of the active layer (4, fig1, [61]).
Re claim 5, Bai modified above teaches the thin film transistor substrate according to claim 1, further comprising: a drain hole (18 holding 10b, fig1, [62]) disposed in the insulating layer (9, 7, 5, fig1, [63]); and a drain electrode (10b, fig1, [62]) disposed on the gate electrode (6 or 8, fig1, [64]) and connected to one side of the active layer (4, fig1, [61]) through the drain hole, wherein a size of the upper hole is larger than a size of the drain hole (forming 18a wider than 18b as in Ban fig2A).
Re claim 6, Bai modified above teaches the thin film transistor substrate according to claim 1, further comprising: a gate insulating layer (7, fig1, [64]) disposed between the active layer (4, fig1, [61]) and the gate electrode (8, fig1, [64]), wherein one end of the gate insulating layer corresponds to one end of the gate electrode (7 between 10a and 8 correspond to left end of 8, fig1), and another end of the gate insulating layer corresponds to another end of the gate electrode (7 between 10b and 8 correspond to right end of 8, fig1), and wherein the insulating layer (9, 7, 5, fig1, [63]) includes an interlayer insulating layer (5, fig1, [63]) that contacts a portion of an upper surface of the active layer (4, fig1, [61]).
Re claim 7, Bai modified above teaches the thin film transistor substrate according to claim 1, wherein the insulating layer (9, 7, 5, fig1, [63]) includes: a gate insulating layer (5, fig1, [63]) disposed between the active layer (4, fig1, [61]) and the gate electrode (6, fig1, [64]) and disposed on an entire surface of the substrate (104, fig1, [67]); and an interlayer insulating layer (9, fig1, [63]) disposed on the gate insulating layer (5, fig1, [63]).
Re claim 9, Bai modified above teaches the thin film transistor substrate according to claim 1, wherein the lower hole (18b, fig3C, [57]) and the upper hole (18a, fig3C, [57]) do not overlap with the gate electrode (6 or 8, fig1, [64]).
Re claim 10, Bai modified above teaches the thin film transistor substrate according to claim 1, wherein the active layer (4, fig1, [61]) includes a channel part (part of 4 between 10a and 10b, fig1, [61]), a first connection part disposed on one side of the channel part (4 around 10a, fig1), and a second connection part (4 around 10b, fig1) disposed on another side of the channel part, and wherein the lower electrode (18b, fig1) is disposed in one of the first connection part (4 around 10a, fig1) and the second connection part (4 around 10b, fig1).
Re claim 22, Bai teaches a thin film transistor substrate (fig1) comprising:
a light blocking layer (2, fig1, [60]) disposed on a substrate (104, fig1, [67]);
an active layer (4, fig1, [61]) overlapping with the light blocking layer;
a first lower hole (18b, fig3C, [57]) penetrating through the active layer;
a gate electrode (6 or 8, fig1, [64]) overlapping with the active layer;
a source electrode (10a, fig1, [62]) penetrating through the active layer and contacting with the light blocking layer;
an insulating layer (9, 7, 5, fig1, [63]) disposed on the active layer; and
a first upper hole (18a, fig1, [57]) penetrating through the insulating layer,
wherein the source electrode (10a, fig1, [62]) includes a first lower electrode (part of 10a in 18b, fig1) disposed in the first lower hole and a first upper electrode (part of 10a in 18a, fig1) disposed in the first upper hole.
Bai does not explicitly show wherein a width of the first upper electrode is greater than a width of the first lower electrode.
Ban teaches a width of the first upper electrode (281, fig2A, [57]) is greater than a width of the first lower electrode (282, fig2A, [57]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Bai and Ban to form the via hole with the process of Ban. The motivation to do so is to reduce process difficulty while increase the contact area between the electrode and the active layer (Ban, [57]).
Re claim 23, Bai modified above teaches the thin film transistor substrate according to claim 22, wherein a center of the first upper hole (18a, fig1, [57]) is aligned with a center of the first lower hole (18b, fig1, [57]).
Claim(s) 1, 4, 12 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Bai et al. CN 114335010A and Lin et al. us 2020/0185532.
Re claim 1, Bai teaches a thin film transistor substrate (fig1) comprising:
a light blocking layer (2, fig1, [60]) disposed on a substrate (104, fig1, [67]);
an active layer (4, fig1, [61]) disposed on the light blocking layer (2, fig1, [60]), the active layer (4, fig1, [61]) including a lower hole (18b, fig3C, [57]) in one side of the active layer;
a gate electrode (6 or 8, fig1, [64]) disposed on the active layer;
a source electrode (10a, fig1, [62]) electrically connected to both of the active layer (4, fig1, [61]) and the light blocking layer (2, fig1, [60]); and
an insulating layer (9, 7, 5, fig1, [63]) disposed between the active layer (4, fig1, [61]) and the source electrode (10a, fig1, [62]), the insulating layer including an upper hole (18a, fig1, [57]),
wherein the source electrode (10a, fig1, [62]) includes a lower electrode (part of 10a in 18b, fig1) disposed in the lower hole (18b, fig3C, [57]) in the active layer (4, fig1, [61]) and an upper electrode (part of 10a in 18a, fig1) disposed in the upper hole (18a, fig3C, [57]) in the insulating layer (9, 7, 5, fig1, [63]),
wherein the active layer (4, fig1, [61]) and the light blocking layer (2, fig1, [60]) are electrically connected to each other through the lower electrode (part of 10a in 18b, fig1), and
Bai does not explicitly show wherein an area of a lower surface of the upper electrode is larger than an area of an upper surface of the lower electrode.
Lin teaches an area of a lower surface of the upper electrode (142, fig3, [23]) is larger than an area of an upper surface of the lower electrode (144a, fig3, [23]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Bai and Lin to form the lower via hole as 144a of Lin. The motivation to do so is to improve conductivity and adhesion between the electrode and the active layer (Lin, [10, 20]).
Re claim 4, Bai modified above teaches the thin film transistor substrate according to claim 1, wherein a distance from one end of the lower surface of the upper electrode to the lower hole is greater than a distance from another end of the lower surface of the upper electrode to the lower hole, or wherein a center of the upper hole does not overlap with a center of the lower hole (Lin, center of 142 not overlap with center of 144a, fig3).
Re claim 12, Bai modified above teaches the thin film transistor substrate according to claim 1, wherein the lower electrode (Lin, 144, fig3, [24]) includes a plurality of lower electrodes (Lin, 144a, fig3, [24]), and wherein each of the plurality of lower electrodes is spaced apart from each other (Lin, fig3).
Re claim 14, Bai modified above teaches the thin film transistor substrate according to claim 12, wherein the upper electrode (Lin, 142, fig3, [23]) extends continuously across at least two adjacent lower electrodes among the plurality of lower electrodes (Lin, 144a, fig3, [24]).
Claim(s) 11 are rejected under 35 U.S.C. 103 as being unpatentable over Bai et al. CN 114335010A, Ban et al. US 2020/0144297 and Yeh et al. US 2013/0087781.
Re claim 11, Bai does not explicitly show the thin film transistor substrate according to claim 1, wherein the active layer includes at least one of an IZO (InZnO)-based oxide semiconductor material, an IGZO (InGaZnO)-based oxide semiconductor material, an IZTO (InZnSnO)-based oxide semiconductor material, and a ZnO-based oxide semiconductor material.
Yeh teaches active layer (240, fig2, [32]) includes at least one of an IZO (InZnO)-based oxide semiconductor material ([32]), an IGZO (InGaZnO)-based oxide semiconductor material ([32]), an IZTO (InZnSnO)-based oxide semiconductor material ([32]), and a ZnO-based oxide semiconductor material ([32]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Bai modified above and Yeh to use a metal oxide material as the active layer. The motivation to do so is to achieve high drain current, low leakage and low subthreshold swing with a high carrier mobility channel material (Yeh, [32]).
Claim(s) 12-13 and 24-27 are rejected under 35 U.S.C. 103 as being unpatentable over Bai et al. CN 114335010A, Ban et al. US 2020/0144297 and Shionoiri et al. US 2008/0001228.
Re claim 12, Bai does not explicitly show the thin film transistor substrate according to claim 1, wherein the lower electrode includes a plurality of lower electrodes, and wherein each of the plurality of lower electrodes is spaced apart from each other.
Shionoiri teaches S/D contact with plurality of electrodes (109, fig7, [84]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Bai modified above and Shionoiri to form 18a and 18b with the shape of Shihionoiri 109. The motivation to do so is to prevent heating of the device during operation and improve reliability of the device (Shionoiri, [259]).
Re claim 13, Bai modified above teaches the thin film transistor substrate according to claim 12, wherein the upper electrode includes a plurality of upper electrodes (Bai 18a in fig1 formed with shape of Shionoiri upper part 109 in layer 156 in fig7), and wherein the plurality of upper electrodes respectively correspond to the plurality of lower electrodes on a one-to-one basis (Bai 18b in fig1 formed with shape of Shionoiri lower part 109 under layer 156 in fig7).
Re claim 24, Bai does not explicitly show the thin film transistor substrate according to claim 22, further comprising: a second lower hole penetrating through the active layer; a third lower hole penetrating through the active layer; and a second upper hole penetrating through the insulating layer, wherein the source electrode is disposed in the first, second and third lower holes and the first and second upper holes.
Shionoiri teaches S/D contact with plurality of electrodes (109, fig7, [84]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Bai modified above and Shionoiri to form 18a and 18b with the shape of Shihionoiri 109. The motivation to do so is to prevent heating of the device during operation and improve reliability of the device (Shionoiri, [259]).
Re claim 25, Bai modified above teaches the thin film transistor substrate according to claim 24, further comprising: a third upper hole penetrating through the insulating layer (Bai 18a in fig1 formed with shape of Shionoiri upper part 109 in layer 156 in fig7), wherein the source electrode (Bai 18 in fig1 formed with shape of Shionoiri 109 in fig7) is disposed in the first, second and third lower holes (Bai 18b in fig1 formed with shape of Shionoiri lower part 109 under layer 156 in fig7) and the first, second and third upper holes (Bai 18a in fig1 formed with shape of Shionoiri upper part 109 in layer 156 in fig7).
Re claim 26, Bai modified above teaches the thin film transistor substrate according to claim 24, wherein the first upper hole is in communication with both of the first lower hole and the second lower hole (Shionoiri, each upper part of 109 in layer 156 electrically connected with all three lower part of 109).
Re claim 27, Bai does not explicitly show the thin film transistor substrate according to claim 22, further comprising: a second lower hole penetrating through the active layer; and a second upper hole penetrating through the insulating layer, wherein the source electrode is disposed in the first and second lower holes and the first and second upper holes.
Shionoiri teaches S/D contact with plurality of electrodes (109, fig7, [84]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Bai modified above and Shionoiri to form 18a and 18b with the shape of Shihionoiri 109. The motivation to do so is to prevent heating of the device during operation and improve reliability of the device (Shionoiri, [259]).
Claim(s) 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over Bai et al. CN 114335010, Ban et al. US 2020/0144297 and Sakai US 2021/0366945.
Re claim 20, Bai teaches a display device (fig1) comprising:
a display area (16, fig1, [47]) and non-display area (19, 20, fig1, [47]) on a substrate (104, fig1, [67]);
a first thin film transistor (TFT with 4, fig1, [61]) disposed on the substrate;
wherein the first thin film transistor (TFT with 4, fig1, [61]) includes:
a first light blocking layer (2, fig1, [60]);
a first active layer (4, fig1, [61]) disposed on the first light blocking layer, the first active layer having a lower hole (18b, fig3C, [57]) in one side of the first active layer;
a first gate electrode (6 or 8, fig1, [64]) disposed on the first active layer;
a first source electrode (10a, fig1, [62]) electrically connected to both of the first active layer and the first light blocking layer; and
an insulating layer (9, 7, 5, fig1, [63]) disposed between the first active layer and the first source electrode, the insulating layer having an upper hole (18a, fig1, [57]),
wherein the first source electrode includes a lower electrode (part of 10a in 18b, fig1) disposed in the lower hole and an upper electrode (part of 10a in 18a, fig1) disposed in the upper hole,
wherein the first active layer (4, fig1, [61]) and the first light blocking layer (2, fig1, [60]) are electrically connected to each other through the lower electrode (part of 10a in 18b, fig1).
Bai does not explicitly show a second thin film transistor having a structure different than a structure of the first thin film transistor, wherein an area of a lower surface of the upper electrode is larger than an area of an upper surface of the lower electrode.
Sakai teaches a second thin film transistor (200, fig1, [42]) having a structure different than a structure of the first thin film transistor (100, fig1, [42]).
Ban teaches an area of a lower surface of the upper electrode (281, fig2A, [57]) is larger than an area of an upper surface of the lower electrode (282, fig2A, [57]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Bai, Sakai and Ban to form the via hole with the process of Ban and form select transistor and drive transistor with different structure. The motivation to do so is to reduce process difficulty while increase the contact area between the electrode and the active layer (Ban, [57]) and adjust the characteristics of devices according to application (Sakai, [3, 81]).
Re claim 21, Bai modified above teaches the display device according to claim 20, wherein the first thin film transistor is a driving thin film transistor disposed in the display area (Sakai, 100, fig1, [81]), and wherein the second thin film transistor is a switching thin film transistor (Sakai, 200, fig1, [81]) disposed in the display area or any one thin film transistor disposed in a gate driver disposed in the non-display area.
Allowable Subject Matter
Claim 8 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim.
Specifically, the limitations are material to the inventive concept of the application in hand to form a subpixel with improved brightness and response time.
Conclusion
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/XIAOMING LIU/Examiner, Art Unit 2812
