Listed by the USPTO as LIU, XIAOMING
Tech Center 2800 • Art Units: 2812
This examiner grants 87% of resolved cases
LIU, XIAOMING is a USPTO patent examiner in Tech Center 2800 and Art Unit 2812. The record includes 615 resolved cases, with an 86.7% allowance rate and a median of 825 days to allowance. The allowance figure indicates that most matters reached allowance, while the median timing suggests a relatively contained prosecution path for this record.
The interview lift is 10.6%, reflecting a positive but limited association between interviews and allowance outcomes. The listed companies are Intel, Taiwan Semiconductor Manufacturing, and Canon. The listed firms are Harrity & Harrity, Schwabe Williamson & Wyatt, and Birch Stewart Kolasch & Birch. Applicants may emphasize strong written claim presentation while using interviews to resolve focused issues.
| App # | Title | Status | Assignee |
|---|---|---|---|
| 18762397 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE | Non-Final OA | SAMSUNG ELECTRONICS CO., LTD. |
| 18423119 | ORGANIC LIGHT EMITTING ELEMENT | Final Rejection | CANON KABUSHIKI KAISHA |
| 17979849 | SEMICONDUCTOR SUBSTRATE AND ELECTRICAL INSPECTION METHOD | Final Rejection | CANON KABUSHIKI KAISHA |
| 18755387 | INTERPOSER INCLUDING LIGHT EMITTING DIODE, METHOD FOR MANUFACTURING INTERPOSER INCLUDING LIGHT EMITTING DIODE, AND METHOD FOR INSPECTING LIGHT EMITTING DIODE | Non-Final OA | LG Display Co., Ltd. |
| 18749931 | THIN FILM TRANSISTOR SUBSTRATE AND METHOD OF MANUFATURING THE SAME AND DISPLAY DEVICE USING THE SAME | Non-Final OA | LG Display Co., Ltd. |
| 18519386 | DISPLAY DEVICE | Final Rejection | Samsung Display Co., LTD. |
| 18596664 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME | Non-Final OA | TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION |
| 18762576 | DISPLAY PANEL, DISPLAY DEVICE, AND METHOD FOR MANUFACTURING DISPLAY PANEL | Non-Final OA | Tianma Advanced Display Technology Institute (Xiamen) Co., Ltd. |
| 18290289 | ENHANCED I/O SEMICONDUCTOR CHIP PACKAGE AND COOLING ASSEMBLY HAVING SIDE I/OS | Final Rejection | Intel Corporation |
| 18216525 | THROUGH GLASS VIAS WITH COMPLIANT LAYER FOR INTEGRATED CIRCUIT DEVICE PACKAGES | Non-Final OA | Intel Corporation |
| 18212382 | INTEGRATED CIRCUIT STRUCTURE WITH DEEP VIA BAR ISOLATION | Non-Final OA | Intel Corporation |
| 18338176 | DIELECTRIC MATERIAL AND A MOLD COMPOUND WITH DIFFERENT DIELECTRIC CONSTANTS COUPLED TO A DIE THAT INCLUDES INTEGRATED CIRCUITRY | Non-Final OA | Intel Corporation |
| 18723662 | ELECTRONIC DEVICE | Non-Final OA | SEMICONDUCTOR ENERGY LABORATORY CO., LTD. |
| 18584470 | MEMORY DEVICES HAVING ADJACENT MEMORY CELLS WITH MITIGATED DISTURB RISK | Non-Final OA | Micron Technology, Inc. |
| 18643589 | POWER MODULE STRUCTURE | Non-Final OA | Delta Electronics, Inc. |
| 18631011 | BACKSIDE GATE TIE DOWN THROUGH BACKSIDE POWER BAR | Non-Final OA | International Business Machines Corporation |
| 18661044 | Method for Attaching Metallic Bodies to Thin Semiconductor Dies at Wafer Level | Non-Final OA | Infineon Technologies AG |
| 18781808 | DOPING ACTIVATION AND OHMIC CONTACT FORMATION IN A SiC ELECTRONIC DEVICE, AND SiC ELECTRONIC DEVICE | Non-Final OA | STMicroelectronics S.r.l. |
| 18785869 | METHODS OF FORMING SEMICONDUCTOR DEVICES | Non-Final OA | Taiwan Semiconductor Manufacturing Company, Ltd. |
| 18783502 | BARRIER LAYER FOR AN INTERCONNECT STRUCTURE | Non-Final OA | Taiwan Semiconductor Manufacturing Company, Ltd. |
| 18590175 | Diffusion Barrier Layers in Semiconductor Devices | Non-Final OA | Taiwan Semiconductor Manufacturing Company, Ltd. |
| 18624655 | PLASMA GENERATING DEVICE, SUBSTRATE PROCESSING APPARATUS, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE | Final Rejection | Kokusai Electric Corporation |
| 18740864 | APPARATUS FORMED FROM ELECTRONIC COMPONENTS HAVING DIFFERENT RESPECTIVE THICKNESSES AND METHODS OF FORMING AN APPARATUS FROM ELECTRONIC COMPONENTS HAVING DIFFERENT RESPECTIVE THICKNESSES | Non-Final OA | Microchip Technology Incorporated |
IP Author analyzes examiner patterns and generates tailored response strategies with the highest chance of allowance.
Build Your Strategy86.7% of resolved applications examined by Xiaoming Liu were allowed (615 resolved cases), compared with 82.1% across Art Unit 2812 over the last five years.
This examiner's interview lift is +10.6 percentage points: the difference in allowance rate between resolved applications that had an examiner interview and those that did not.
Applications allowed by Xiaoming Liu took 825 days on average from filing to allowance.
Xiaoming Liu examines applications in Art Unit 2812 in Tech Center 2800 (Semiconductors, Circuits & Optics).
