DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 7 is objected to because of the following informalities: there is typographical error in typing the limitation “veiw” rather it should be “view”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6 and 9-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hung et al. (US 2021/0193550 A1 hereinafter referred to as “Hung”).
With respect to claim 1, Hung discloses, in Figs.1A-10, a semiconductor package, comprising: a package substrate (100) including a plurality of wiring layers (123, 133, 115) and a plurality of insulating layers (121, 131, 111) covering a portion of the plurality of wiring layers (123, 133, 115) (see Par.[0022] wherein the core layer 110 may include a dielectric layer 111 having through holes 113 which cross the dielectric layer 111 from side to side; the through holes 113 are filled by the through vias 115; each build-up layer 120 or 130 respectively includes a dielectric layer 121 or 131 and conductive patterns 123 or 133 embedded in the corresponding dielectric layer 121 or 131 and providing electrical connection between opposite sides of the corresponding dielectric layer 121 or 131); and a semiconductor chip (200) mounted on the package substrate (100), wherein at least a first insulating layer (121), among the plurality of insulating layers, comprises a first insulating member filling first (523B1)and second/(entire region defined by substrate 100) regions and wherein a second insulating member filling a third region (513B), wherein the first region has a first wiring layer/(wiring in first region), among the plurality of wiring layers, and has first sides corresponding to edges of the package substrate (100) and second sides between the first sides corresponding to corners of the package substrate (100), wherein the second region is disposed between the first sides of the first region and the edges of the package substrate (100), and wherein the third region (513B) is disposed between the second sides of the first region and the corners of the package substrate (100) (see Par.[0044] wherein the lid 523B of the metallic cover 503B may include a region 523B1 of thickness T1 (as illustrated, e.g., in FIG. 1F) on the semiconductor package 200 and extending further than the semiconductor package 200 on both directions D1 and D2; along the direction D2, the region 523B1 may reach the outer flanges 513B everywhere in correspondence of the span of the semiconductor package 200; along the direction D1, the region 523B1 may reach the outer flanges 513B in between the grooves 533B1 and reach the grooves 533B2 elsewhere; the lid 523B may reach a thickness T2 (as illustrated, e.g., in FIG. 1F) in correspondence of the grooves 533B1, 533B2, and include a region 523B2 of thickness greater than T2 in between the grooves 533B1, 533B2 and the outer flanges 513B).
With respect to claim 2, Hung discloses, in Figs.1A-10, the semiconductor package, wherein the second insulating member overlaps at least a portion of a second wiring layer (133) on a different level from the first wiring layer (123) along a vertical direction (see Fig.4A).
With respect to claim 3, Hung discloses, in Figs.1A-10, the semiconductor package, wherein the second insulating member comprises prepreg (see Par.[0022] wherein the core layer 110 may include a dielectric layer 111 having through holes 113 which cross the dielectric layer 111 from side to side; it is submitted that prepreg is a dielectric material (such as the core dielectric 111 in Hung) used in PCBs to provide electrical insulation and bond layers together).
Moreover, regarding the limitation “the second insulating member comprises prepreg”, it is submitted that prepreg is a composite material consisting of reinforcement fibers pre-impregnated with a partially cured resin, ready for molding and final curing. As such, the said limitation does not further define the structure as instantly claimed, nor serve to distinguish over Hung. Therefore, the said claimed limitation is a “product by process” limitation. Applicant attention is thereby directed to the fact that a "product by process" claim is directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wertheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Marosi et al, 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or not. Note that applicant has the burden of proof in such cases, as the above case law make clear.
With respect to claim 4, Hung discloses, in Figs.1A-10, the semiconductor package, wherein the package substrate has four of the edges and four of the corners in a plan view (see Fig.2G).
With respect to claim 5, Hung discloses, in Figs.1A-10, the semiconductor package, wherein the first insulating member covers a portion of the plurality of wiring layers (see Fig.1G).
With respect to claim 6, Hung discloses, in Figs.1A-10, the semiconductor package, wherein a length of each of the first sides is longer than a length of each of the second sides (see Figs.2B-2H).
With respect to claim 9, Hung discloses, in Figs.1A-10, the semiconductor package, wherein the first region and the third region are in contact with each other in a plan view (see Fig.1G).
With respect to claim 10, Hung discloses, in Figs.1A-10, the semiconductor package, wherein the second region has a shorter length than a length of the edges of the package substrate (see Fig.1G).
With respect to claim 11, Hung discloses, in Figs.1A-10, the semiconductor package, further comprising: a heat dissipation member (510A) surrounding the semiconductor chip, on the package substrate (see Par.[0034] wherein a footprint of the metallic cover 500A substantially matches and is aligned with the footprint of the circuit substrate 100; the metallic cover 500A includes outer flanges 510A and a lid 520A; the outer flanges 510A may be disposed at the periphery of the lid 520A; an outer edge 510out of the flanges 510A is vertically aligned with an outer edge 100e of the circuit substrate 100).
With respect to claim 12, Hung discloses, in Figs.1A-10, a semiconductor package, comprising: a package substrate (100) including a plurality of insulating layers (111, 121, 131) and a plurality of wiring layers (123, 115, 133); a semiconductor chip (200) disposed on the package substrate (100); and a heat dissipating member (520A, 510A) spaced apart from the semiconductor chip (200) along a horizontal direction and disposed on the package substrate (100), wherein on a plane, the package substrate has a patterned region including a central portion of the package substrate, a non-patterned region disposed around the patterned region and having a first side in contact with the patterned region, and an insulating region disposed on both sides of the non-patterned region and having a second side in contact with the patterned region and the non-patterned region, and wherein a length of a perpendicular line drawn from an adjacent apex of the package substrate to the second side is longer than a length of a perpendicular line drawn from an adjacent side surface of the package substrate to the first side (see Par.[0022] wherein the core layer 110 may include a dielectric layer 111 having through holes 113 which cross the dielectric layer 111 from side to side; the through holes 113 are filled by the through vias 115; each build-up layer 120 or 130 respectively includes a dielectric layer 121 or 131 and conductive patterns 123 or 133 embedded in the corresponding dielectric layer 121 or 131 and providing electrical connection between opposite sides of the corresponding dielectric layer 121 or 131; see Par.[0044] wherein the lid 523B of the metallic cover 503B may include a region 523B1 of thickness T1 (as illustrated, e.g., in FIG. 1F) on the semiconductor package 200 and extending further than the semiconductor package 200 on both directions D1 and D2; along the direction D2, the region 523B1 may reach the outer flanges 513B everywhere in correspondence of the span of the semiconductor package 200; along the direction D1, the region 523B1 may reach the outer flanges 513B in between the grooves 533B1 and reach the grooves 533B2 elsewhere; the lid 523B may reach a thickness T2 (as illustrated, e.g., in FIG. 1F) in correspondence of the grooves 533B1, 533B2, and include a region 523B2 of thickness greater than T2 in between the grooves 533B1, 533B2 and the outer flanges 513B; see Par.[0034] wherein a footprint of the metallic cover 500A substantially matches and is aligned with the footprint of the circuit substrate 100; the metallic cover 500A includes outer flanges 510A and a lid 520A; the outer flanges 510A may be disposed at the periphery of the lid 520A; an outer edge 510out of the flanges 510A is vertically aligned with an outer edge 100e of the circuit substrate 100).
With respect to claim 13, Hung discloses, in Figs.1A-10, the semiconductor package, wherein the plurality of wiring layers (123, 133, 115) overlap the second side along a vertical direction (see Fig.1G).
With respect to claim 14, Hung discloses, in Figs.1A-10, a semiconductor package comprising: a package substrate (100); a semiconductor chip (200) disposed on the package substrate (100); a heat dissipating member (510A, 520A) disposed on the package substrate (100) and surrounding the semiconductor chip (200), wherein the package substrate further comprises: an insulating layer (111); upper wiring layers (123) disposed above the insulating layer (111) and lower wiring layers (133) disposed below the insulating layer (111); and an upper insulating layer (121) and a lower insulating layer (131) covering the upper and lower wiring layers, respectively, wherein one of the upper insulating layer and the lower insulating layer comprises a first portion/(middle portion) covering the upper wiring layers or the lower wiring layers, and a second portion/(extremity portions) disposed at both ends of the first portion in a first direction and spaced apart from the upper wiring layers or the lower wiring layers disposed in the first portion in a horizontal direction, wherein the other of the upper insulating layer and the lower insulating layer comprises a third portion/(package corners portions) covering the upper wiring layers or the lower wiring layers, and wherein a width of the first portion along the first direction is smaller than a width of the third portion along the first direction (see Par.[0022] wherein the core layer 110 may include a dielectric layer 111 having through holes 113 which cross the dielectric layer 111 from side to side; the through holes 113 are filled by the through vias 115; each build-up layer 120 or 130 respectively includes a dielectric layer 121 or 131 and conductive patterns 123 or 133 embedded in the corresponding dielectric layer 121 or 131 and providing electrical connection between opposite sides of the corresponding dielectric layer 121 or 131; see Par.[0044] wherein the lid 523B of the metallic cover 503B may include a region 523B1 of thickness T1 (as illustrated, e.g., in FIG. 1F) on the semiconductor package 200 and extending further than the semiconductor package 200 on both directions D1 and D2; along the direction D2, the region 523B1 may reach the outer flanges 513B everywhere in correspondence of the span of the semiconductor package 200; along the direction D1, the region 523B1 may reach the outer flanges 513B in between the grooves 533B1 and reach the grooves 533B2 elsewhere; the lid 523B may reach a thickness T2 (as illustrated, e.g., in FIG. 1F) in correspondence of the grooves 533B1, 533B2, and include a region 523B2 of thickness greater than T2 in between the grooves 533B1, 533B2 and the outer flanges 513B; see Par.[0034] wherein a footprint of the metallic cover 500A substantially matches and is aligned with the footprint of the circuit substrate 100; the metallic cover 500A includes outer flanges 510A and a lid 520A; the outer flanges 510A may be disposed at the periphery of the lid 520A; an outer edge 510out of the flanges 510A is vertically aligned with an outer edge 100e of the circuit substrate 100; see Figs.2B-2E wherein corners portions 501B, length and width of package are shown).
With respect to claim 15, Hung discloses, in Figs.1A-10, the semiconductor package, wherein the second portion overlaps the upper wiring layers or the lower wiring layers disposed in the third portion along a vertical direction (see Fig1G).
With respect to claim 16, Hung discloses, in Figs.1A-10, the semiconductor package, wherein the first portion and the second portion comprise the same insulating material (see Fig1G).
With respect to claim 17, Hung discloses, in Figs.1A-10, the semiconductor package, wherein the first portion and the second portion comprise prepreg (see Par.[0022] wherein the core layer 110 may include a dielectric layer 111 having through holes 113 which cross the dielectric layer 111 from side to side; it is submitted that prepreg is a dielectric material (such as the core dielectric 111 in Hung) used in PCBs to provide electrical insulation and bond layers together).
Moreover, regarding the limitation “the second insulating member comprises prepreg”, it is submitted that prepreg is a composite material consisting of reinforcement fibers pre-impregnated with a partially cured resin, ready for molding and final curing. As such, the said limitation does not further define the structure as instantly claimed, nor serve to distinguish over Hung. Therefore, the said claimed limitation is a “product by process” limitation. Applicant attention is thereby directed to the fact that a "product by process" claim is directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wertheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Marosi et al, 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or not. Note that applicant has the burden of proof in such cases, as the above case law make clear.
With respect to claim 18, Hung discloses, in Figs.1A-10, the semiconductor package, wherein the first portion and the second portion have the same height (see Fig.1G).
Claims 1-6, 9-11, 14-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim (US 2023/0106013 A1).
With respect to claim 1, Kim discloses, in Figs.1-14D, a semiconductor package, comprising: a package substrate (100) including a plurality of wiring layers (111) and a plurality of insulating layers (110) covering a portion of the plurality of wiring layers (111) (see Par.[0084]-[0089] wherein the package substrate 100 may be substantially the same as the wiring substrate 10 and include the dielectric layers 110, the via patterns 111, the internal circuit patterns 113a and 113b, the lower and upper wiring patterns 123 and 133, the lower and upper conductive pads 125 and 135, and the lower and upper plating patterns 141 and 151); and a semiconductor chip (200) mounted on the package substrate (100), wherein at least a first insulating layer/(upper dielectric 110 in region 10U) (110_10U), among the plurality of insulating layers (110), comprises a first insulating member filling first (10U) and second/(entire region or 100) (SL and 10U) regions and wherein a second insulating member/(upper dielectric 110 in region SL) (110_SL) filling a third region (SL), wherein the first region has a first wiring layer (111, 113a), among the plurality of wiring layers, and has first sides corresponding to edges of the package substrate (100) and second sides between the first sides corresponding to corners of the package substrate (100), wherein the second region (10U and SL) is disposed between the first sides of the first region and the edges of the package substrate (100), and wherein the third region (SL) is disposed between the second sides of the first region and the corners of the package substrate (100) (see Par.[0025]-[0028] wherein the internal circuit patterns 113a and 113b may be formed between the dielectric layers 110 on each unit region 10U; the wiring substrate 10 may include a plurality of unit regions 10U, a sawing region SL that surrounds, e.g., an entire perimeter of, each of the unit regions 10U, and an edge region ER that surrounds the, e.g., combined entire perimeter of the, unit regions 10U and the sawing region SL).
With respect to claim 2, Kim discloses, in Figs.1-14D, the semiconductor package, wherein the second insulating member overlaps at least a portion of a second wiring layer (110, 113b) on a different level from the first wiring layer along a vertical direction (see Figs.8, 13, Par.[0028] wherein the internal circuit patterns 113a and 113b may be formed between the dielectric layers 110 on each unit region 10U).
With respect to claim 3, Kim discloses, in Figs.1-14D, the semiconductor package, wherein the second insulating member comprises prepreg (see Par.[0029] wherein the dielectric layer 110 may include prepreg, Ajinomoto build-up film (ABF), flame retardant 4 (FR-4), or bismaleimide triazine (BT)).
With respect to claim 4, Kim discloses, in Figs.1-14D, the semiconductor package, wherein the package substrate has four of the edges and four of the corners in a plan view (see Fig.8).
With respect to claim 5, Kim discloses, in Figs.1-14D, the semiconductor package, wherein the first insulating member covers a portion of the plurality of wiring layers (see Fig.8).
With respect to claim 6, Kim discloses, in Figs.1-14D, the semiconductor package, wherein a length of each of the first sides is longer than a length of each of the second sides (see Figs.4-5, 8).
With respect to claim 9, Kim discloses, in Figs.1-14D, the semiconductor package, wherein the first region and the third region are in contact with each other in a plan view (see Figs.4-5, 8).
With respect to claim 10, Kim discloses, in Figs.1-14D, the semiconductor package, wherein the second region has a shorter length than a length of the edges of the package substrate (see Figs.4-5, 8).
With respect to claim 11, Kim discloses, in Figs.1-14D, the semiconductor package, further comprising: a heat dissipation member (300) surrounding the semiconductor chip, on the package substrate (see Par.[0084] wherein a semiconductor package may include a package substrate 100, at least one semiconductor chip 200, and a molding layer 300).
With respect to claim 14, Kim discloses, in Figs.1-14D, a semiconductor package comprising: a package substrate (100); a semiconductor chip (200) disposed on the package substrate (100); a heat dissipating member (300) disposed on the package substrate and surrounding the semiconductor chip, wherein the package substrate further comprises: an insulating layer/(middle 110); upper wiring layers (111, 113a) disposed above the insulating layer (110) and lower wiring layers (111, 113b) disposed below the insulating layer (110); and an upper insulating layer and a lower insulating layer covering the upper and lower wiring layers, respectively, wherein one of the upper insulating layer and the lower insulating layer comprises a first portion/(middle portion overlapping with chip) covering the upper wiring layers or the lower wiring layers, and a second portion/(portion outside chip area) disposed at both ends of the first portion in a first direction and spaced apart from the upper wiring layers or the lower wiring layers disposed in the first portion in a horizontal direction, wherein the other of the upper insulating layer and the lower insulating layer comprises a third portion/(package corners portion) covering the upper wiring layers or the lower wiring layers, and wherein a width of the first portion along the first direction is smaller than a width of the third portion along the first direction (see Par.[0084]-[0089] wherein the package substrate 100 may be substantially the same as the wiring substrate 10 and include the dielectric layers 110, the via patterns 111, the internal circuit patterns 113a and 113b, the lower and upper wiring patterns 123 and 133, the lower and upper conductive pads 125 and 135, and the lower and upper plating patterns 141 and 151; see Par.[0025]-[0028] wherein the internal circuit patterns 113a and 113b may be formed between the dielectric layers 110 on each unit region 10U; the wiring substrate 10 may include a plurality of unit regions 10U, a sawing region SL that surrounds, e.g., an entire perimeter of, each of the unit regions 10U, and an edge region ER that surrounds the, e.g., combined entire perimeter of the, unit regions 10U and the sawing region SL; see Par.[0084] wherein a semiconductor package may include a package substrate 100, at least one semiconductor chip 200, and a molding layer 300; see Figs.4, 10A wherein corners areas of package, length and width of package are shown).
With respect to claim 15, Kim discloses, in Figs.1-14D, the semiconductor package, wherein the second portion overlaps the upper wiring layers or the lower wiring layers disposed in the third portion along a vertical direction (see Figs.4-5, 8).
With respect to claim 16, Kim discloses, in Figs.1-14D, the semiconductor package, wherein the first portion and the second portion comprise the same insulating material (see Figs.4-5, 8).
With respect to claim 17, Kim discloses, in Figs.1-14D, the semiconductor package, wherein the first portion and the second portion comprise prepreg (see Par.[0029] wherein the dielectric layer 110 may include prepreg, Ajinomoto build-up film (ABF), flame retardant 4 (FR-4), or bismaleimide triazine (BT)).
With respect to claim 18, Kim discloses, in Figs.1-14D, the semiconductor package, wherein the first portion and the second portion have the same height (see Figs.4-5, 8).
With respect to claim 19, Kim discloses, in Figs.1-14D, the semiconductor package, wherein the upper wiring layers and the lower wiring layers comprise copper (Cu) (see Par.[0031] wherein the via patterns 111 may be formed in the dielectric layers 110 before the internal circuit patterns 113a and 113b are formed; the internal circuit patterns 113a and 113b and the via patterns 111 may include, e.g., one of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or a combination thereof).
Claims 1-2, 4-11, 14-16, 18-19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Park et al. (US 2023/0131730 A1 hereinafter referred to as “Park”).
The applied reference has a common assignee: Samsung Electronics Co., Ltd. with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
With respect to claim 1, Park discloses, in Figs.1-12, a semiconductor package, comprising: a package substrate (110) including a plurality of wiring layers (112-113) and a plurality of insulating layers (111) covering a portion of the plurality of wiring layers (112-113) (see Par.[0019]-[0023] wherein the package substrate 110 may be a printed circuit board (PCB) The package substrate 110 may include a base substrate 118 having a front surface S1 and a rear surface S2 disposed in opposite directions, and front pads 114 and rear pads 115 respectively disposed on the front surface S1 and the rear surface S2, a front protective layer 116 having front openings FO respectively exposing the front pads 114 and covering the front surface S1, a rear protective layer 117 having rear openings BO exposing the rear pads 115 and covering the rear surface S2; the base substrate 118 may include a plurality of insulating layers 111 and a plurality of redistribution layers 112 disposed in the plurality of insulating layers 111, and redistribution vias 113); and a semiconductor chip (120) mounted on the package substrate (110), wherein at least a first insulating layer (111a), among the plurality of insulating layers (111), comprises a first insulating member/() (111a) filling first (AR2) and second/(entire area of package) regions and wherein a second insulating member (111a) filling a third region (AR1), wherein the first region (AR2) has a first wiring layer (111a), among the plurality of wiring layers (111), and has first sides corresponding to edges of the package substrate (110) and second sides between the first sides corresponding to corners of the package substrate (110), wherein the second region is disposed between the first sides of the first region and the edges of the package substrate (110), and wherein the third region (AR1) is disposed between the second sides of the first region and the corners of the package substrate (110) (see Par.[0028] wherein the mounting region AR may include first regions AR1 adjacent to the first to fourth corners C1, C2, C3, and C4, respectively, and a second area AR2 other than the first regions AR1; the second region AR2 may be disposed to divide the first regions AR1 into at least two groups; for example, when the mounting region AR has a quadrangular shape, the first regions AR1 may include four regions to be adjacent to the first to fourth edges E1, E2, E3, and E4 of the mounting region AR, respectively, and the second region AR2 may be disposed in a +-shape dividing the first regions AR1, respectively; also, according to an example embodiment, the first regions AR1 may include two regions adjacent to the two of the first to fourth edges E1, E2, E3, and E4 of the mounting region AR).
With respect to claim 2, Park discloses, in Figs.1-12, the semiconductor package, wherein the second insulating member overlaps at least a portion of a second wiring layer on a different level from the first wiring layer along a vertical direction (see Figs.11-12).
With respect to claim 4, Park discloses, in Figs.1-12, the semiconductor package, wherein the package substrate has four of the edges and four of the corners in a plan view (see Figs.3B-9, 11-12).
With respect to claim 5, Park discloses, in Figs.1-12, the semiconductor package, wherein the first insulating member covers a portion of the plurality of wiring layers (see Figs.11-12).
With respect to claim 6, Park discloses, in Figs.1-12, the semiconductor package, wherein a length of each of the first sides is longer than a length of each of the second sides (see Figs.3B-9, 11-12).
With respect to claim 7, Park discloses, in Figs.1-12, the semiconductor package, wherein the first region has an octagon shape formed by the first sides and the second sides in a plan view (see Fig.9).
With respect to claim 8, Park discloses, in Figs.1-12, the semiconductor package, wherein the third region has a triangular shape formed by corresponding sides of the corners of the package substrate and the edges of the package substrate in a plan view (see Fig.9).
With respect to claim 9, Park discloses, in Figs.1-12, the semiconductor package, wherein the first region and the third region are in contact with each other in a plan view (see Figs.3B-9, 11-12).
With respect to claim 10, Park discloses, in Figs.1-12, the semiconductor package, wherein the second region has a shorter length than a length of the edges of the package substrate (see Figs.3B-9, 11-12).
With respect to claim 11, Park discloses, in Figs.1-12, the semiconductor package, further comprising: a heat dissipation member (150, 116) surrounding the semiconductor chip (120), on the package substrate (110) (see Par.[0042] wherein the encapsulant 150 may include or be formed of, for example, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a prepreg, ABF, FR-4, BT, and an epoxy molding compound (EMC) including an inorganic filler or/and glass fiber; see Par.[0031]-[0032] wherein the front protective layer 116 and the rear protective layer 117 may be disposed to cover the front surface S1 and the rear surface S2 of the base substrate 118, respectively).
With respect to claim 14, Park discloses, in Figs.1-12, a semiconductor package comprising: a package substrate (110); a semiconductor chip (120) disposed on the package substrate (110); a heat dissipating member (150) disposed on the package substrate (110) and surrounding the semiconductor chip (120), wherein the package substrate further comprises: an insulating layer (111c); upper wiring layers (112-113) disposed above the insulating layer (111c) and lower wiring layers (112-113) disposed below the insulating layer (111c); and an upper insulating layer (111a) and a lower insulating layer (111b) covering the upper and lower wiring layers (112-113), respectively, wherein one of the upper insulating layer and the lower insulating layer comprises a first portion/(portion underlying and overlapping the chip) covering the upper wiring layers or the lower wiring layers, and a second portion/(portions outside chip areas) disposed at both ends of the first portion in a first direction and spaced apart from the upper wiring layers or the lower wiring layers disposed in the first portion in a horizontal direction, wherein the other of the upper insulating layer and the lower insulating layer comprises a third portion (AR1) covering the upper wiring layers or the lower wiring layers, and wherein a width of the first portion along the first direction is smaller than a width of the third portion along the first direction (see Par.[0019]-[0023] wherein the package substrate 110 may be a printed circuit board (PCB) The package substrate 110 may include a base substrate 118 having a front surface S1 and a rear surface S2 disposed in opposite directions, and front pads 114 and rear pads 115 respectively disposed on the front surface S1 and the rear surface S2, a front protective layer 116 having front openings FO respectively exposing the front pads 114 and covering the front surface S1, a rear protective layer 117 having rear openings BO exposing the rear pads 115 and covering the rear surface S2; the base substrate 118 may include a plurality of insulating layers 111 and a plurality of redistribution layers 112 disposed in the plurality of insulating layers 111, and redistribution vias 113; see Par.[0028] wherein the mounting region AR may include first regions AR1 adjacent to the first to fourth corners C1, C2, C3, and C4, respectively, and a second area AR2 other than the first regions AR1; the second region AR2 may be disposed to divide the first regions AR1 into at least two groups; for example, when the mounting region AR has a quadrangular shape, the first regions AR1 may include four regions to be adjacent to the first to fourth edges E1, E2, E3, and E4 of the mounting region AR, respectively, and the second region AR2 may be disposed in a +-shape dividing the first regions AR1, respectively; also, according to an example embodiment, the first regions AR1 may include two regions adjacent to the two of the first to fourth edges E1, E2, E3, and E4 of the mounting region AR; see Par.[0042] wherein the encapsulant 150 may include or be formed of, for example, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a prepreg, ABF, FR-4, BT, and an epoxy molding compound (EMC) including an inorganic filler or/and glass fiber; see Par.[0031]-[0032] wherein the front protective layer 116 and the rear protective layer 117 may be disposed to cover the front surface S1 and the rear surface S2 of the base substrate 118, respectively; see Figs.3B-9 wherein corners areas of package, length and width are shown).
With respect to claim 15, Park discloses, in Figs.1-12, the semiconductor package, wherein the second portion overlaps the upper wiring layers or the lower wiring layers disposed in the third portion along a vertical direction (see Figs.3B-9, 11-12).
With respect to claim 16, Park discloses, in Figs.1-12, the semiconductor package, wherein the first portion and the second portion comprise the same insulating material (see Figs.3B-9, 11-12).
With respect to claim 18, Park discloses, in Figs.1-12, the semiconductor package, wherein the first portion and the second portion have the same height (see Figs.3B-9, 11-12).
With respect to claim 19, Park discloses, in Figs.1-12, the semiconductor package, wherein the upper wiring layers and the lower wiring layers comprise copper (Cu) (see Par.[0061] wherein the connection structure 140 may extend in a vertical direction (Z-axis direction) between the package substrate 110 and the interposer substrate 130, to provide a vertical connection path electrically connecting the redistribution layer 112 and the upper interconnection layer 132; the connection structure 140 may have a spherical or ball shape made of a low-melting point metal such as tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), lead (Pb), or an alloy (e.g., Sn—Ag—Cu) including thereof).
Allowable Subject Matter
Claim 20 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Citation of Pertinent Prior Art
The prior art made of record (e.g.; see PTO-892) and not relied upon is considered pertinent to applicant's disclosure.
Examiner’s Telephone/Fax Contacts
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOULOUCOULAYE INOUSSA whose telephone number is (571)272-0596. The examiner can normally be reached Monday-Friday (10-18).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JEFF W NATALINI can be reached at 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Mouloucoulaye Inoussa/ Primary Examiner, Art Unit 2818
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