DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed July 28, 2026 have been fully considered.
The applicant argues in “a”, “b”, and “c” that Kato does not teach the cited limitations. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). The examiner, in the rejection of May 14, 2026, discusses the teachings of Kato in paragraph 10, but also discusses how the combination of Yoshida and Kato in paragraph 12 teaches the limitations the applicant cites as not being taught by Kato (alone).
In “d”, the applicant argues Yoshida is not directed to chamfered wafers and one of ordinary skill in the art would not look to combine aspects from the two references. The examiner maintains the rationale for obviousness and that techniques related to ensuring high accuracy in manufacturing silicon wafers that are chamfered may also be applied to other shapes of silicon wafers.
In “e”, the applicant argues that Kato is non-analogous art with respect to Yoshida as they are directed to solving different problems that are not related. The applicant misapplies the requirement that to rely on a reference under 35 U.S.C 103 it must be analogous art to the claimed invention (the requirement is relative to the claimed invention not to the other art), see MPEP 2141.01(a). Therefore, the applicant’s allegation is moot.
Assuming the applicant intended to argue that Kato is non-analogous to the claimed invention, to be successful the applicant would have to argue that Kato is both:
not from the same field of endeavor as the claimed invention
not reasonably pertinent to the problem faced by the inventor
The examiner finds that Kato is in the field of endeavor of wafer manufacturing which is the same field of endeavor as the claimed invention. The same is also true of Yoshida.
In “f”, the applicant argues that impermissible hindsight is used as there is allegedly no teaching or suggestion for the combination of Yoshida and Kato. The examiner disagrees and maintains the rationale presented in paragraph 11 of the action of May 14, 2026.
In “g”, the applicant argues that the combination of Yoshida and Kato would result in a wafer with a flat interior portion with precisely contoured chamfered edges. The examiner disagrees, as the manufacturing principles/steps of Yoshida of using test wafters, measuring the results of the test wafers, performing a correction processing step, and then subsequent manufacture of the product wafers is applied to wafer production disclosed by Yoshida. This is in contrast to simply precisely controlling a chamfered edge as alleged by applicant.
The applicant does not provide further arguments against the rejection of claim 2.
New claim 4 is rejected under 35 U.S.C 112(a) and 35 U.S.C 103 as shown in the rejections below.
The rejections are final as the only changes to the rejections are to address the new claim.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 4 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 4 recites, “a test grinding step of grinding a whole surface of the test grinding wafer”. The applicant has not cited a portion of the disclosure that supports the new claim. The examiner finds there is no support for this limitation as there is no disclosure related to the test grinding step including grinding the whole surface of the test grinding wafer.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Yoshida et al. (JP2008060470) hereinafter Yoshida in view of Kato (U.S Pre-Grant Publication 20090170406) hereinafter Kato.
Regarding claim 1, Yoshida discloses:
A wafer grinding method in which a chuck table mounted to a table base is made to communicate with a suction source and a wafer held under suction by a holding surface of the chuck table is ground by a wafer grinding grindstone for grinding the wafer {Figure 3, chuck table (20) is mounted to table base (8). A wafer (W) is held under suction by a holding surface (21) of the chuck table is ground by a wafer grinding grindstone (31); ]0016][0017]/[0036]},
the wafer grinding method comprising:
a holding surface forming step of grinding an upper surface of the chuck table by use of the wafer grinding grindstone or a table griding grindstone for grinding the table in a state in which the chuck table does not communicate with the suction source, to thereby form the holding surface {Holding surface grinding step is performed; [0028]. Figure 11 (31) grinds the upper surface of the chuck table which is the holding surface (21). The suction is only used when grinding the wafer; [0017]};
a holding step of causing the holding surface to communicate with the suction source and holding a test grinding wafer under suction by the holding surface, after the holding surface forming step is carried out {Figure 15, (W) is held against (21)[0017]/[0036]};
a grinding step of holding a product wafer under suction by the holding surface and grinding the product wafer to a predetermined thickness with the wafer grinding grindstone {Wafter grinding step is performed while under suction by the holding surface (21), grinding the wafer (W) to a predetermined thickness using grindstone (31); [0031]/[0036]},
Yoshida does not explicitly disclose:
a test grinding step of grinding the test grinding wafer held under suction by the holding surface in the holding step by the wafer grinding grindstone to a predetermined thickness;
a distribution measuring step of measuring a thickness distribution of a whole surface of the test grinding wafer ground in the test grinding step, or an upper surface height distribution of a whole surface of an upper surface of the test grinding wafer;
a holding surface correction processing step of subjecting the holding surface used in the test grinding step to correction processing in such a manner that a holding surface having a surface shape similar to that of the upper surface of the test grinding wafer having been ground is obtained, in reference to the thickness distribution or the upper surface height distribution measured in the distribution measuring step; and
the grinding step being performed after the holding surface correction processing step is carried out.
Kato pertains to semiconductor wafer manufacturing / grinding. Kato teaches:
a test grinding step of grinding the test grinding wafer {Figure 1, steps (C) and (D); the dummy wafer is a test wafer; [0069-[0071]};
a distribution measuring step of measuring a thickness distribution of the test grinding wafer {Figure 1, step (e); [0072]};
a correction processing step of subjecting a surface used in the test grinding step to correction processing {Figure 1, steps (f) and (g); [0073]-[0080]}; and
the grinding step being performed after the holding surface correction processing step is carried out {Figure 1, step (h) of the grinding of the product is performed after a dummy/test wafer; [0082]}.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have used the general principles of manufacturing taught by Kato of using test wafers, measuring the results of the test wafers, performing a correction processing step, and then subsequently manufacturing the product wafers for the wafer manufacturing of Yoshida. One of ordinary skill in the art would be motivated to do so to improve the accuracy of the manufacturing efficiently {Kato [0015]}.
The combination of Yoshida and Kato therefore teaches:
a test grinding step of grinding the test grinding wafer held under suction by the holding surface in the holding step by the wafer grinding grindstone to a predetermined thickness {The wafer grinding of Yoshida [0031]/[0036] which uses suction is applied to a test wafer based on the teachings of Kato Figure 1 steps (c) and (d)};
a distribution measuring step of measuring a thickness distribution of a whole surface of the test grinding wafer ground in the test grinding step, or an upper surface height distribution of a whole surface of an upper surface of the test grinding wafer {The measurement step of Kato Figure 1 (e) described in [0072] is applied to the wafer grinding of Yoshida. At least the entire upper surface of the test grinding wafer would need to be measured to ensure the uniform thickness desired by Yoshida [0012]/[0036]};
a holding surface correction processing step of subjecting the holding surface used in the test grinding step to correction processing in such a manner that a holding surface having a surface shape similar to that of the upper surface of the test grinding wafer having been ground is obtained, in reference to the thickness distribution or the upper surface height distribution measured in the distribution measuring step {The measurement step (e) of Kato is used in the evaluation and correction steps (f) and (g). When these steps are applied to the grinding operation of Yoshida the correction would be applied to the grinding of the holding surface of Yoshida. The surface is the key surface that is shaped to ensure a uniform thickness of the water and it is explicitly recognized by Yoshida as needing to be corrected; [0012]/[0028]/[0033]. The examiner finds that holding surface has a surface shape similar to that the of upper surface of the test grinding wafer. It is noted that term similar may be interpreted quite broadly under a broadest reasonable interpretation}; and
the grinding step being performed after the holding surface correction processing step is carried out {Kato Figure 1 step (h) teaches that the product wafers are processed after the validation and correction of the test wafers is complete. This concept is applied to the grinding steps of Yoshida}.
Regarding claim 4, Yoshida discloses:
A wafer grinding method in which a chuck table mounted to a table base is made to communicate with a suction source and a wafer held under suction by a holding surface of the chuck table is ground by a wafer grinding grindstone for grinding the wafer {Figure 3, chuck table (20) is mounted to table base (8). A wafer (W) is held under suction by a holding surface (21) of the chuck table is ground by a wafer grinding grindstone (31); ]0016][0017]/[0036]},
the wafer grinding method comprising:
a holding surface forming step of grinding an upper surface of the chuck table by use of the wafer grinding grindstone or a table griding grindstone for grinding the table in a state in which the chuck table does not communicate with the suction source, to thereby form the holding surface {Holding surface grinding step is performed; [0028]. Figure 11 (31) grinds the upper surface of the chuck table which is the holding surface (21). The suction is only used when grinding the wafer; [0017]};
a holding step of causing the holding surface to communicate with the suction source and holding a test grinding wafer under suction by the holding surface, after the holding surface forming step is carried out {Figure 15, (W) is held against (21)[0017]/[0036]};
a grinding step of holding a product wafer under suction by the holding surface and grinding the product wafer to a predetermined thickness with the wafer grinding grindstone {Wafter grinding step is performed while under suction by the holding surface (21), grinding the wafer (W) to a predetermined thickness using grindstone (31); [0031]/[0036]},
Yoshida does not explicitly disclose:
a test grinding step of grinding a whole surface of the test grinding wafer held under suction by the holding surface in the holding step by the wafer grinding grindstone to a predetermined thickness;
a distribution measuring step of measuring a thickness distribution of the whole surface of the test grinding wafer ground in the test grinding step, or an upper surface height distribution of a whole surface of an upper surface of the test grinding wafer;
a holding surface correction processing step of subjecting the holding surface used in the test grinding step to correction processing in such a manner that a holding surface having a surface shape similar to that of the upper surface of the test grinding wafer having been ground is obtained, in reference to the thickness distribution or the upper surface height distribution measured in the distribution measuring step; and
the grinding step being performed after the holding surface correction processing step is carried out.
Kato pertains to semiconductor wafer manufacturing / grinding. Kato teaches:
a test grinding step of grinding the test grinding wafer {Figure 1, steps (C) and (D); the dummy wafer is a test wafer; [0069-[0071]};
a distribution measuring step of measuring a thickness distribution of the test grinding wafer {Figure 1, step (e); [0072]};
a correction processing step of subjecting a surface used in the test grinding step to correction processing {Figure 1, steps (f) and (g); [0073]-[0080]}; and
the grinding step being performed after the holding surface correction processing step is carried out {Figure 1, step (h) of the grinding of the product is performed after a dummy/test wafer; [0082]}.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have used the general principles of manufacturing taught by Kato of using test wafers, measuring the results of the test wafers, performing a correction processing step, and then subsequently manufacturing the product wafers for the wafer manufacturing of Yoshida. One of ordinary skill in the art would be motivated to do so to improve the accuracy of the manufacturing efficiently {Kato [0015]}.
The combination of Yoshida and Kato therefore teaches:
a test grinding step of grinding a whole surface of the test grinding wafer held under suction by the holding surface in the holding step by the wafer grinding grindstone to a predetermined thickness {The wafer grinding of Yoshida [0031]/[0036] which uses suction is applied to a test wafer based on the teachings of Kato Figure 1 steps (c) and (d). The wafer itself may be only considered W1/W3 and therefore the grinding is applied to this whole surface. Alternatively, the wafer may include W2/W4 as well, but the whole surface only includes the surface of W1/W3};
a distribution measuring step of measuring a thickness distribution of the whole surface of the test grinding wafer ground in the test grinding step, or an upper surface height distribution of a whole surface of an upper surface of the test grinding wafer {The measurement step of Kato Figure 1 (e) described in [0072] is applied to the wafer grinding of Yoshida. At least the entire upper surface of the test grinding wafer would need to be measured to ensure the uniform thickness desired by Yoshida [0012]/[0036]};
a holding surface correction processing step of subjecting the holding surface used in the test grinding step to correction processing in such a manner that a holding surface having a surface shape similar to that of the upper surface of the test grinding wafer having been ground is obtained, in reference to the thickness distribution or the upper surface height distribution measured in the distribution measuring step {The measurement step (e) of Kato is used in the evaluation and correction steps (f) and (g). When these steps are applied to the grinding operation of Yoshida the correction would be applied to the grinding of the holding surface of Yoshida. The surface is the key surface that is shaped to ensure a uniform thickness of the water and it is explicitly recognized by Yoshida as needing to be corrected; [0012]/[0028]/[0033]. The examiner finds that holding surface has a surface shape similar to that the of upper surface of the test grinding wafer. It is noted that term similar may be interpreted quite broadly under a broadest reasonable interpretation}; and
the grinding step being performed after the holding surface correction processing step is carried out {Kato Figure 1 step (h) teaches that the product wafers are processed after the validation and correction of the test wafers is complete. This concept is applied to the grinding steps of Yoshida}.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Yoshida in view of Kato as applied to claim 1 above, and in further view of Gokita (U.S Pre-Grant Publication 20210074537) hereinafter Gokita, Yanagisawa et al. (U.S Patent 6,451,217) hereinafter Yanagisawa, and Melzner et al. (U.S Patent 5,964,652) hereinafter Melzner.
Regarding claim 2, the combination of Yoshida and Kato teaches the wafer grinding method of claim 1. The combination of Yoshida and Kato is silent regarding the material of the chuck table, and therefore is silent regarding:
wherein the holding surface of the chuck table includes silicon
Also, the combination of Yoshida and Kato does not teach:
in the holding surface correction processing step, partially plasmatized etching gas is jetted from an etching gas jet nozzle to the holding surface to subject the holding surface to correction processing by atmospheric-pressure plasma etching.
Gokita pertains to wafer grinding. Gokita teaches:
wherein the holding surface of the chuck table includes silicon {[0053]}
Since the combination of Yoshida and Kato is silent regarding the material of the holding surface of the chuck table, one of ordinary skill in the art would have to choose. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have chosen silicon for the material of the chuck table of the combination of Yoshida and Kato based on the teachings of Gokita. One of ordinary skill in the art would be motivated to do so as it increases the ease of machining {Gokita [0053]}.
Yanagisawa silicon wafer manufacturing. Yanagisawa teaches:
partially plasmatized etching gas is jetted from an etching gas jet nozzle to a surface to subject the surface to processing by atmospheric-pressure plasma etching {Column 10 lines 60-67}.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have used atmospheric-pressure plasma etching from a jet nozzle to perform the holding surface correction step of the combination of Yoshida, Kato, and Gokita. One of ordinary skill in the art would be motivated to do so as plasma etching can be performed and the silicon material of the holding surface to a high degree of precision that is useful in a correction step which requires a high precision {Gokita [0053]; Melzner Column 1 lines 37-49}.
The combination of Yoshida, Kato, Gokita, Yanagisawa, and Melzner therefore teaches:
in the holding surface correction processing step, partially plasmatized etching gas is jetted from an etching gas jet nozzle to the holding surface to subject the holding surface to correction processing by atmospheric-pressure plasma etching {Atmospheric-pressure plasma etching from a jet nozzle to perform of the teachings of Yanagisawa is used for the holding surface correction step as described in the rejection of claim 1}.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL K. REITZ whose telephone number is (571)272-1387. The examiner can normally be reached M-F 7:30 a.m. -5:30 p.m.
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/MICHAEL K. REITZ/Examiner, Art Unit 3745
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