Prosecution Insights
Last updated: October 27, 2026
Application No. 18/750,090

3-DIMENSIONAL ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THE SAME

Non-Final OA §102
Filed
Jun 21, 2024
Priority
Aug 24, 2023 — RE 10-2023-0111131
Examiner
JUNG, MICHAEL YOO LIM
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Electronics and Telecommunications Research Institute
OA Round
1 (Non-Final)
83%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allowance Rate
1072 granted / 1295 resolved
+14.8% vs TC avg
Moderate +10% lift
Without
With
+10.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
22 currently pending
Career history
1326
Total Applications
across all art units

Statute-Specific Performance

§101
2.4%
-37.6% vs TC avg
§103
30.7%
-9.3% vs TC avg
§102
33.4%
-6.6% vs TC avg
§112
28.8%
-11.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1295 resolved cases

Office Action

§102
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION In response to a restriction requirement mailed on 07/15/2026, the Applicant elected Invention II (Group II) drawn to a 3-dimensional electronic device encompassing claims 11-19, without traverse on 09/08/2026. Non-elected Invention I (Group I) drawn to a method encompassing claims 1-10 is withdrawn. Elected device claims 11-19 are examined below. Priority Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement (IDS) Two information disclosure statement submitted on 06/21/2024 (“06-21-24 IDS”) and 12/03/2024 (“12-03-24 IDS”) are in compliance with the provisions of 37 CFR 1.97. Accordingly, the 06-21-24 IDS and 12-03-24 IDS are being considered by the examiner. Specification The specification is objected to, because the title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: 3-DIMENSIONAL ELECTRONIC DEVICE HAVING SIDE WIRES WITHIN MOLD LAYER CONFIGURED TO CONNECT VIA ELECTRODE OF GUIDE BLOCK AND METHOD FOR MANUFACTURING THE SAME Claim Rejections - 35 USC § 1021 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Claims 11 and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pub. No. US 2013/0341803 A1 to Cheah et al. ("Cheah"). Figs. 2A-2D of Cheah have been provided to support the rejections below: [AltContent: textbox (Mold2)][AltContent: ][AltContent: textbox (Mold1)][AltContent: ][AltContent: ][AltContent: textbox (Chip2)][AltContent: textbox (Chip1)][AltContent: ][AltContent: textbox (SUB2)][AltContent: textbox (SUB1)][AltContent: ][AltContent: ] PNG media_image1.png 515 576 media_image1.png Greyscale PNG media_image2.png 209 468 media_image2.png Greyscale Regarding independent claim 11, Cheah teaches a 3-dimensional electronic device (see Figs. 2A-2E for example. Fig. 2A has been annotated to support the rejections below) comprising: a plurality of substrates SUB1, SUB2; semiconductor chips Chip1, Chip2 on each of the plurality of substrates SUB1, SUB2; guide blocks 201 (para [0024] - “an intermediate vertical side chip (i-VSC) 201”) may be coupled to the MSD structures 220 and 221, as described in greater detail below.” Portions of the 201 that is between active layer 202 and the solder ball 262.) provided on sidewalls of the substrates SUB1, SUB2 and having via electrodes 270 (para [0025] - “one or more through silicon vias (TSVs) 270 includes in the -i-VSC 201, as depicted in FIGS. 2A, 2B and 2C.”); upper mold layers Mold1, Mold2 provided between the semiconductor chips Chip1, Chip2 and the substrates SUB1, SUB2; upper wires (para [0020] - “Corresponding active layers 123, 125, 127, 129, 131, 133 and 135 are also shown.”) provided within the upper mold layers Mold1, Mold2, and configured to connect the semiconductor chips Chip1, Chip2 to each other; side mold layers 202 (para [0024] - “an active layer 202.” Fig. 2B shows multiple layers within the active layer 202.) on sidewalls of the upper mold layers Mold1, Mold2 and the guide blocks 201; side wires provided within the side mold layers 202, and configured to connect the via electrodes 270 of the guide blocks 201 to each other. Regarding claim 12, Cheah teaches the semiconductor chips Chip1, Chip2 that have pads 236 (para [0025] - “…Die side pad structures, such as die side pad structure 236…”) that are exposed from the substrate SUB1 or SUB2. Allowable Subject Matter The following is a statement of reasons for the indication of allowable subject matter: Claim 13 is objected to for depending on a rejected base claim 11, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 11 or the base claim 11 is amended to include all of the limitations of claim 13. Claim 14 is objected to for depending on a rejected base claim 11, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 11 or the base claim 11 is amended to include all of the limitations of claim 14. Claim 15 is objected to for depending on a rejected base claim 11, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 11 or the base claim 11 is amended to include all of the limitations of claim 15. Claims 16-18 are allowable for depending from the allowable claim 15. Claim 19 is allowable for depending from the allowable claim 14. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Pub. No. US 2025/0062278 A1 to Suthram et al. Patent No. US 11,990,449 B2 to Kim Pub. No. US 2023/0378047 A1 to Sowwan et al. Pub. No. US 2020/0312769 A1 to Pon et al. Pub. No. US 2020/0075542 A1 to Sung et al. Pub. No. US 2018/0366429 A1 to Chiu et al. Pub. No. US 2015/0014860 A1 to Jang et al. Pub. No. US 2013/0292842 A1 to Kim Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL JUNG whose telephone number is (408) 918-7554. The examiner can normally be reached on 8:30 A.M. to 7 P.M. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached on (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MICHAEL JUNG/Primary Examiner, Art Unit 2817 13 October 2026 1 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Read full office action

Prosecution Timeline

Jun 21, 2024
Application Filed
Oct 16, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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SEMICONDUCTOR DEVICE AND METHOD OF FORMING A SEMICONDUCTOR DEVICE
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Patent 12765298
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3y 0m to grant Granted Oct 13, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
83%
Grant Probability
93%
With Interview (+10.5%)
2y 4m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1295 resolved cases by this examiner. Grant probability derived from career allowance rate.

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