DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of invention Group I, Species I (FIG. 4), Species D (FIG. 10), Species 1 (FIG. 11), and Species J (FIGs. 30 & 3) in the reply filed on 8/7/2026 is acknowledged.
Claim 5 reciting “the resin is provided from the second region through the side surface” pertains to a feature shown in FIGs. 31-33 directed to non-elected Species K and L.
Claim 8 reciting “a shape of an opening of the recesses is larger than a shape of a bottom of the recesses” pertains to a feature shown in FIGs. 5-6 directed to non-elected Species II-III.
Claim 10 reciting “a part of the resin adjoins a metal that has a same composition as the first pad at the interface that has the recesses and protrusions” pertains to a feature shown in FIG. 33 directed to non-elected Species L.
Claim 11 reciting “the first pad includes a first metal layer and a second metal layer provided between the first metal layer and the insulating layer, and a third metal layer that has a same composition as the second metal layer is exposed in surfaces of the recesses” pertains to a feature shown in FIGs. 39-40 directed to non-elected Species IV.
Claims 15-20 reciting “a method of manufacturing a semiconductor device” pertains to non-elected invention Group II.
Therefore, claims 5, 8, 10-11, and 15-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention and species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 8/7/2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 6-7, 9, and 12-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kwon et al. US 2019/0043833 A1 (Kwon).
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In re claim 1, Kwon discloses (e.g. FIGs. 1-3) a semiconductor device, comprising:
a first semiconductor chip 100 that has a first (top) surface 101 including a first region (center region of 101) and a second region 101E adjacent to the first region;
a second semiconductor chip 200C provided on the first (center) region; and
resin 300 provided on the second region 101E and adjoining the second semiconductor chip 200C, wherein at least a part of an interface between the first semiconductor chip 100 and the resin 300 has recesses and protrusions 150 (¶ 21).
In re claim 2, Kwon discloses (e.g. FIGs. 1-3) wherein the second semiconductor chip 200C is bonded to the first (center) region of the first surface 101 of the first semiconductor chip 100,
the second region 101E of the first surface 101 of the first semiconductor chip 100 includes recesses 151 at a bonding plane (plane at top surface 101 of chip 100) between the first semiconductor chip 100 and the second semiconductor chip 200C, and
the resin 300 has a protruding portion 305 that occupies at least a part of the recesses 151 (see FIG. 2, ¶ 24).
In re claim 3, Kwon discloses (e.g. FIGs. 1-2) further comprising:
a first pad 121,110 on the first surface 101 of the first semiconductor chip 100,
a second pad 251 on the second semiconductor chip 200C,
the first pad 121,110 and the second pad 251 are joined so as to bond the first semiconductor chip 100 and the second semiconductor chip 200,
a shape of section perpendicular to the first pad 121,110 is the same as a shape of section perpendicular to the protruding portion 305 (both the pads 121,110 and the protruding portion 305 has a rectangular shape in a cross section as shown in FIGs. 1 and 2).
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In re claim 4, Kwon discloses (e.g. FIGs. 1-3) wherein the first semiconductor chip 100 has a first side (left side) and a second side (right side) that are opposite to each other when the first surface 101 is viewed in plan view (FIG. 3) along a direction perpendicular to the first surface 101,
the first region (a region of 101 as annotated in FIG. 3 above, on which chip 200C is at least partially provided) is located nearer to the first (left) side than the second (right) side,
the second region (left edge region 101E) includes a third region (region including 150 on the left edge region) located between the first (left) side and the first region (see FIG. 3 above), and the interface in at least a part of the third region includes the recesses and protrusions 150.
In re claim 6, Kwon discloses (e.g. FIGs. 1-3) wherein the second region 101E of the first semiconductor chip 100 includes recesses 151 at a bonding plane (plane at top surface 101 of chip 100) between the first semiconductor chip 100 and the second semiconductor chip 200C, and
the recesses 151 have a geometrical pattern when the first surface 101 of the first semiconductor chip 100 is viewed in plan view along a direction perpendicular to the first surface 101 (see FIG. 3 shown geometrical pattern 151).
In re claim 7, Kwon discloses (e.g. FIGs. 1-3) wherein the second region 101E of the first semiconductor chip 100 includes recesses 151 at a bonding plane (plane at top surface 101 of chip 100) between the first semiconductor chip 100 and the second semiconductor chip 200C, and
the recesses 151 include a rectangular, circular, or elliptical outline when the first surface 101 of the first semiconductor chip 100 is viewed in plan view along a direction perpendicular to the first surface 101 (see FIG. 3 showing recesses 151 with rectangular outline).
In re claim 9, Kwon discloses (e.g. FIGs. 1-3) wherein the second region 101E of the first semiconductor chip 100 includes recesses 151 at a bonding plane (plane at top surface 101 of chip 100) between the first semiconductor chip 100 and the second semiconductor chip 200C, and
a shape of an opening of the recesses 151 and a shape of a bottom of the recesses 151 are substantially same (see FIG. 3 showing recesses 151 having linear side surfaces 151S and same width W at top and bottom of the recesses 151).
In re claim 12, Kwon discloses (e.g. FIGs. 1-3) wherein the first semiconductor chip 100 includes silicon (¶ 29).
In re claim 13, Kwon discloses (e.g. FIGs. 1-3) wherein the second semiconductor chip 200C includes a plurality of stacked memory chips 200 (¶ 32).
In re claim 14, Kwon discloses (e.g. FIGs. 1-3) wherein at least a part of a top surface 200TS of the second semiconductor chip 200C is exposed from the resin 300 when the first surface is viewed in plan view along a direction perpendicular to the first surface.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2020/0357766 (FIG. 3) teaches bottom chip 10 having edge regions 10E with recesses and protrusions.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU CHEN whose telephone number is (571)270-7881. The examiner can normally be reached Monday-Friday: 9AM-5PM ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, WILLIAM KRAIG can be reached on 5712728660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YU CHEN/Primary Examiner, Art Unit 2896
YU CHEN
Examiner
Art Unit 2896
Prosecution Insights