DETAILED ACTION
This Office Action is in response to the applicant's application filed June 21st, 2024. In virtue of this communication, claims 1-23 are currently presented in the instant application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 5, 6, 12, 13, 17, 20, and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Oh et al. (US 2016/0063924 A1; hereinafter Oh).
With respect to claim 1, Oh teaches a display device in Figs. 5, 12, and 13, comprising:
a substrate SUB having a display area AA and a non-display area NA adjacent to the display area AA (see Figs. 5, 12, 13, and paragraphs 40, 147, 149);
a first semiconductor layer (comprising SA1, A1, DA1) and a second semiconductor layer (comprising SA2, A2, DA2) on the substrate SUB (see Fig. 5 and paragraphs 41-43, 46, 97, 98), the first semiconductor layer (comprising SA1, A1, DA1) disposed in the non-display area NA and including a polycrystalline semiconductor material (see Figs. 5, 13, and paragraphs 42, 46, 97, 154, 161; note T1 used for GIP at NA in Fig. 13), and the second semiconductor layer (comprising SA2, A2, DA2) disposed in the display area AA and including an oxide semiconductor material (see Figs. 5, 13, and paragraphs 43, 47, 98, 154, 161; note T2 used for ST at AA in Fig. 13);
a first gate insulating layer GI2 on the first semiconductor layer (comprising SA1, A1, DA1) and the second semiconductor layer (comprising SA2, A2, DA2) (see Fig. 5 and paragraphs 94, 97, 98);
a first gate electrode G1 and a second gate electrode G2 on the first gate insulating layer GI2, the first gate electrode G1 and the second gate electrode G2 corresponding to the first semiconductor layer (comprising SA1, A1, DA1) and the second semiconductor layer (comprising SA2, A2, DA2), respectively (see Fig. 5 and paragraphs 97, 98);
a first interlayer insulating layer ILD on the first gate electrode G1 and the second gate electrode G2 (see Fig. 5 and paragraphs 99, 100, 110); and
a first source electrode S1, a first drain electrode D1, a second source electrode S2 and a second drain electrode D2 on the first interlayer insulating layer ILD, the first source electrode S1 and the first drain electrode D1 coupled to both end portions, respectively, of the first semiconductor layer (comprising SA1, A1, DA1), the second source electrode S2 and the second drain electrode D2 coupled to both end portions, respectively, of the second semiconductor layer (comprising SA2, A2, DA2) (see Fig. 5 and paragraphs 100, 111, 112).
With respect to claim 2, Oh teaches the display device of claim 1, wherein the first semiconductor layer (comprising SA1, A1, DA1) and the second semiconductor layer (SA2, A2, DA2) have a same layer as each other (see Fig. 5 and paragraphs 41-43, 46, 97, 98; note both semiconductor layers have source and drain layers).
With respect to claim 5, Oh teaches the display device of claim 1, further comprising a second gate insulating layer GI1 on the first semiconductor layer (comprising SA1, A1, DA1), wherein the second semiconductor layer (comprising SA2, A2, DA2) is disposed on the second gate insulating layer GI1 (see Fig. 5 and paragraphs 94-97).
With respect to claim 6, Oh teaches the display device of claim 1, further comprising a second gate insulating layer GI1 on the first semiconductor layer (comprising SA1, A1, DA1) and under the second semiconductor layer (comprising SA2, A2, DA2) (see Fig. 5 and paragraphs 94-97).
With respect to claim 12, Oh teaches a display device in Figs. 5, 12, and 13, comprising:
a substrate SUB having a display area AA and a non-display area NA adjacent to the display area AA (see Figs. 5, 12, 13, and paragraphs 40, 147, 149);
a first semiconductor layer (comprising SA1, A1, DA1) on the substrate SUB at the non-display area NA (see Figs. 5, 13, and paragraphs 41-43, 46, 97, 98, 154, 161; note T1 used for GIP at NA in Fig. 13);
a second semiconductor layer (comprising SA2, A2, DA2) on the substrate SUB at the display area AA (see Figs. 5, 13, and paragraphs 41-43, 46, 97, 98, 154, 161; note T2 used for ST at AA in Fig. 13);
a first gate insulating layer GI2 adjacent to the first semiconductor layer (comprising SA1, A1, DA1) and the second semiconductor layer (comprising SA2, A2, DA2), the first gate insulating layer GI2 extending from the first semiconductor layer (comprising SA1, A1, DA1) at the non-display area NA to the second semiconductor layer (comprising SA2, A2, DA2) at the display area AA (see Figs. 5, 13, and paragraphs 94, 97, 98, 154, 155);
a second gate insulating layer GI1 on the first gate insulating layer (comprising SA1, A1, DA1) (see Fig. 5 and paragraphs 94-97);
a first gate electrode G1 and a second gate electrode G2 on the second gate insulating layer GI2 (see Fig. 5 and paragraphs 97, 98);
a first interlayer insulating layer ILD on the first gate electrode G1 and the second gate electrode G2 (see Fig. 5 and paragraphs 99, 100, 110); and
a first source electrode S1 and a first drain electrode D1 on the first interlayer insulating layer ILD at the non-display area NA (see Figs. 5, 13, and paragraphs 100, 111, 112, 154, 161);
a second source electrode S2 and a second drain electrode D2 on the first interlayer insulating layer ILD at the display area AA (see Figs. 5, 13, and paragraphs 100, 111, 112, 154, 161); and
a light emitting diode OLE including a first electrode ANO, a second electrode CAT, and an emitting layer OL between the first and second electrodes (see Fig. 13 and paragraphs 151-154),
wherein the first electrode ANO of the light emitting diode OLE is coupled to either the second source electrode S2 or the second drain electrode D2 in the display area AA (see Figs. 5, 13, and paragraphs 53, 152, 155, 156; note in paragraph 53 the pixel electrode anode connected to D2).
With respect to claim 13, Oh teaches the display device of claim 12, further comprising: a first buffer layer BUF between the substrate SUB and the first (comprising SA1, A1, DA1) and second (comprising SA2, A2, DA2) semiconductor layers, wherein the first buffer layer BUF continuously and contiguously extends from the first semiconductor layer (comprising SA1, A1, DA1) in the non-display area NA to the second semiconductor layer (comprising SA2, A2, DA2) in the display area AA, wherein the first buffer layer BUF overlaps both the first semiconductor layer (comprising SA1, A1, DA1) in the non-display area NA and the second semiconductor layer (comprising SA2, A2, DA2) in the display area AA from a plan view (see Figs. 5, 13, and paragraphs 41-43, 94, 95, 154, 161; note T1 used for GIP at NA and T2 used for ST at AA in Fig. 13).
With respect to claim 17, Oh teaches the display device of claim 12, wherein the first gate insulating layer GI2 is disposed on and contacting the first semiconductor layer (comprising SA1, A1, DA1) at the non-display area NA, and wherein the second semiconductor layer (comprising SA2, A2, SA2) is disposed on and contacting the first gate insulating layer GI2 at the display area AA (see Fig. 5 and paragraphs 94-97).
With respect to claim 20, Oh teaches the display device of claim 12, wherein the first semiconductor layer (comprising SA1, A1, DA1) disposed in the non-display area NA includes a polycrystalline semiconductor material (see Figs. 5, 13, and paragraphs 42, 46, 97, 154, 161; note T1 used for GIP at NA in Fig. 13), and the second semiconductor layer (comprising SA2, A2, DA2) disposed in the display area AA includes an oxide semiconductor material (see Figs. 5, 13, and paragraphs 43, 47, 98, 154, 161; note T2 used for ST at AA in Fig. 13).
With respect to claim 21, Oh teaches the display device of claim 12, wherein the first gate insulating layer GI2 continuously and contiguously extends from the first semiconductor layer (comprising SA1, A1, DA1) at the non-display area NA to the second semiconductor layer (comprising SA2, A2, DA2) at the display area AA, and wherein the first gate insulating layer GI2 overlaps the first semiconductor layer (comprising SA1, A1, DA1) at the non-display area NA and the second semiconductor layer (comprising SA2, A2, DA2) at the display area AA from a plan view (see Figs. 5, 13, and paragraphs 94, 97, 98, 154, 155).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 22, and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Oh et al. (US 2016/0063924 A1; hereinafter Oh) in view of Je et al. (US 2020/0168638 A1; hereinafter Je).
With respect to claim 3, Oh discloses the display device of claim 2, further comprising: a first buffer layer BUF between the substrate SUB and the first semiconductor layer (comprising SA1, A1, DA1) and between the substrate SUB and the second semiconductor layer (comprising SA2, A2, DA2) (see Figs. 5, 13, and paragraphs 41-43, 94, 95, 154, 161; note T1 used for GIP at NA and T2 used for ST at AA in Fig. 13); a first planarizing layer PAS and a second planarizing layer PL sequentially on the first interlayer insulating layer ILD (see Figs. 5, 13, and paragraphs 99, 100, 101, 110, 156, 160, 161; PAS and PL sequentially formed on ILD of T1 as GIP and T2 as ST); and a light emitting diode OLE on the second planarizing layer PL (see Fig. 13 and paragraphs 151-154, 156).
Oh does not disclose a display device comprising a second buffer layer, a second interlayer insulating layer, or a storage capacitor between the first gate insulating layer and the second buffer layer, or a first encapsulating layer, a second encapsulating layer, and a third encapsulating layer sequentially on the light emitting diode.
Je discloses a display device in Fig. 2 comprising a second buffer layer (of 314) and a second interlayer insulating layer (of 314) (see Fig. 2 and paragraphs 95 and note 314 made of multiple layers; same material same properties), a storage capacitor 340 between a first gate insulating layer 313 and the second buffer layer (of 314) (see Fig. 2 and paragraphs 84, 90, 91, 95), a first encapsulating layer 361, a second encapsulating layer 362, and a third encapsulating layer 363 sequentially on a light emitting diode 350 (see Fig. 2 and paragraphs 83, 84, 109).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the display device of Oh would comprise a second buffer layer, a second interlayer insulating layer, a storage capacitor between the first gate insulating layer and the second buffer layer as taught by Je because such layers and configurations are well known in the art and would have been an obvious matter of design choice since the applicant has not disclosed that the extra layers and configuration solve any problems or are for a particular reason. Additionally, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the display device of Oh would comprise a first encapsulating layer, a second encapsulating layer, and a third encapsulating layer sequentially on the light emitting diode as taught by Je because it is well known in the art to include such encapsulating layers to protect the underlaying light emitting diode layers (see MPEP 2144 I).
With respect to claim 22, Oh discloses the display device of claim 12.
Oh does not disclose a capacitor having a first capacitor electrode and a second capacitor electrode on the first capacitor electrode; a second drain extending electrode coupled to the second drain electrode; and a second source extending electrode coupled to the second source electrode, wherein the second source extending electrode horizontally extends towards the capacitor and overlaps the second capacitor electrode from a plan view.
Je discloses a display device in Fig. 1 further comprising: a capacitor 140 having a first capacitor electrode 141 and a second capacitor electrode 142 on the first capacitor electrode 141; a second drain extending electrode 132 coupled to the second drain electrode 131b; and a second source extending electrode 133 coupled to the second source electrode 131c, wherein the second source extending electrode 133 horizontally extends towards the capacitor 140 and overlaps the second capacitor electrode 142 from a plan view (see Fig. 1 and paragraphs 36, 49, 52, 54, 55; note source drain labels change depending on design choice).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the display device of Oh would further comprise: a capacitor having a first capacitor electrode and a second capacitor electrode on the first capacitor electrode; a second drain extending electrode coupled to the second drain electrode; and a second source extending electrode coupled to the second source electrode, wherein the second source extending electrode horizontally extends towards the capacitor and overlaps the second capacitor electrode from a plan view as taught by Je so that the first gate electrode of the first thin-film transistor, the second gate electrode of the second thin-film transistor, and the first capacitor electrode of the storage capacitor can be formed via a single process on the same layer, so that the processing steps can be reduced. Additionally, the fabrication cost can be saved by reducing the processing time (see Je: paragraph 17).
With respect to claim 23, the combination of Oh and Je discloses the display device of claim 22, wherein a portion 150 of the second source extending electrode 133 that horizontally extended toward the capacitor 140 vertically extends towards the second capacitor electrode 142 to make an electrical connection (see Je: Fig. 1 and paragraphs 36, 67, 69).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Oh et al. (US 2016/0063924 A1; hereinafter Oh) in view of Je et al. (US 2020/0168638 A1; hereinafter Je) as applied to claim 3 above, and further in view of Ono et al. (US 2021/0305353 A1; hereinafter Ono).
With respect to claim 4, the combination of Oh and Je disclose the display device of claim 3.
The combination does not disclose: a first gate extending electrode and a second gate extending electrode coupled to the first gate electrode and the second gate electrode, respectively; and a capacitor extending electrode coupled to the storage capacitor, wherein the first gate extending electrode, the first source electrode, the first drain electrode, the second gate extending electrode, the second source electrode and the second drain electrode are disposed on the second interlayer insulating layer and have a same layer and a same material as each other.
Ono discloses a display device in at least Figs. 3 and 4 further comprising: a first gate extending electrode (SD1 for OGE) and a second gate extending electrode (SD1 for GE1) coupled to the first gate electrode OGE and the second gate electrode GE1, respectively; and a capacitor extending electrode (SD1 for CST) coupled to the storage capacitor CST, wherein the first gate extending electrode (SD1 for OGE), a first source electrode (SD1 at 372 left), a first drain electrode (SD1 at 372 right), the second gate extending electrode (SD1 for GE1), a second source electrode (SD1 at 370 left) and a second drain electrode (SD1 at 370 right) are disposed on a second interlayer insulating layer OILD and have a same layer (all include SD1) and a same material as each other (see Figs. 3, 4, and paragraphs 7, 42-44, 48).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the display device of the combination of Oh and Je would further comprise: a first gate extending electrode and a second gate extending electrode coupled to the first gate electrode and the second gate electrode, respectively; and a capacitor extending electrode coupled to the storage capacitor, wherein the first gate extending electrode, the first source electrode, the first drain electrode, the second gate extending electrode, the second source electrode and the second drain electrode are disposed on the second interlayer insulating layer and have a same layer and a same material as each other as taught by Ono to allow for proper electrical interconnection (see MPEP 2144 I). Additionally, by having the different electrodes made of a same material, the cost and time of manufacturing are reduced when the plurality of extending electrodes are all made of the same material (see MPEP 2144 I).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Oh et al. (US 2016/0063924 A1; hereinafter Oh) in view of Ono et al. (US 2021/0305353 A1; hereinafter Ono).
With respect to claim 8, Oh discloses the display device of claim 1.
Oh does not disclose a first gate extending electrode and a second gate extending electrode on the first interlayer insulating layer, wherein the first gate extending electrode and the second gate extending electrode are coupled to the first gate electrode and the second gate electrode, respectively, and wherein the first gate extending electrode, the first source electrode, the first drain electrode, the second gate extending electrode, the second source electrode and the second drain electrode are disposed on the first interlayer insulating layer and have a same layer and a same material as each other.
Ono discloses a display device in at least Figs. 3 and 4 further comprising a first gate extending electrode (SD1 for OGE) and a second gate extending electrode (SD1 for GE1) on a first interlayer insulating layer OILD, wherein the first gate extending electrode (SD1 for OGE) and the second gate extending electrode (SD1 for GE1) are coupled to a first gate electrode OGE and second gate electrode GE1, respectively, and wherein the first gate extending electrode (SD1 for OGE0, first source electrode (SD1 at 372 left), a first drain electrode (SD1 at 372 right), the second gate extending electrode (SD1 for GE1), a second source electrode (SD1 at 370 left) and a second drain electrode (SD1 at 370 right) are disposed on the first interlayer insulating layer OILD and have a same layer (all include SD1) and a same material as each other (see Figs. 3, 4, and paragraphs 7, 42-44, 48).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the display device of Oh would further comprise a first gate extending electrode and a second gate extending electrode on the first interlayer insulating layer, wherein the first gate extending electrode and the second gate extending electrode are coupled to the first gate electrode and the second gate electrode, respectively, and wherein the first gate extending electrode, the first source electrode, the first drain electrode, the second gate extending electrode, the second source electrode and the second drain electrode are disposed on the first interlayer insulating layer and have a same layer and a same material as each other as taught by Ono to allow for proper electrical interconnection (see MPEP 2144 I). Additionally, by having the different electrodes made of a same material, the cost and time of manufacturing are reduced when the plurality of extending electrodes are all made of the same material (see MPEP 2144 I).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Oh et al. (US 2016/0063924 A1; hereinafter Oh) and Ono et al. (US 2021/0305353 A1; hereinafter Ono) as applied to claim 8 above, and further in view of Je et al. (US 2020/0168638 A1; hereinafter Je).
With respect to claim 9, the combination of Oh and Ono discloses the display device of claim 8, further comprising: a first buffer layer BUF between the substrate SUB and the first semiconductor layer (comprising SA1, A1, DA1) and between the substrate SUB and the second semiconductor layer (comprising SA2, A2, DA2) (see Oh: Figs. 5, 13, and paragraphs 41-43, 94, 95, 154, 161; note T1 used for GIP at NA and T2 used for ST at AA in Fig. 13); a first planarizing layer PAS and a second planarizing layer PL sequentially on the first interlayer insulating layer ILD (see Oh: Figs. 5, 13, and paragraphs 99, 100, 101, 110, 156, 160, 161; PAS and PL sequentially formed on ILD of T1 as GIP and T2 as ST); a light emitting diode OLE on the second planarizing layer PL (see Oh: Fig. 13 and paragraphs 151-154, 156).
The combination does not disclose a display device comprising a second buffer layer, or a storage capacitor between the first gate insulating layer and the second buffer layer, or a first encapsulating layer, a second encapsulating layer, and a third encapsulating layer sequentially on the light emitting diode.
Je discloses a display device in Fig. 2 comprising a second buffer layer (of 314) (see Fig. 2 and paragraphs 95 and note 314 made of multiple layers; same material same properties), a storage capacitor 340 between a first gate insulating layer 313 and the second buffer layer (of 314) (see Fig. 2 and paragraphs 84, 90, 91, 95), a first encapsulating layer 361, a second encapsulating layer 362, and a third encapsulating layer 363 sequentially on a light emitting diode 350 (see Fig. 2 and paragraphs 83, 84, 109).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the display device of Oh would comprise a second buffer layer, a storage capacitor between the first gate insulating layer and the second buffer layer as taught by Je because such layers and configurations are well known in the art and would have been an obvious matter of design choice since the applicant has not disclosed that the extra layers and configuration solve any problems or are for a particular reason. Additionally, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the display device of Oh would comprise a first encapsulating layer, a second encapsulating layer, and a third encapsulating layer sequentially on the light emitting diode as taught by Je because it is well known in the art to include such encapsulating layers to protect the underlaying light emitting diode layers (see MPEP 2144 I).
Allowable Subject Matter
Claims 7, 10, 11, 14-16, 18, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art does not disclose or fairly suggest:
wherein the first semiconductor layer and the second gate insulating layer on the first semiconductor layer have a same shape as each other, and wherein the second semiconductor layer and the second gate insulating layer under the second semiconductor layer have a same shape as each other, as called for in claim 7;
a first source extending electrode, a first drain extending electrode, a second source extending electrode and a second drain extending electrode coupled to the first source electrode, the first drain electrode, the second source electrode and the second drain electrode, respectively, wherein the first source extending electrode, the first drain extending electrode, the second source extending electrode and the second drain extending electrode are disposed on the first planarizing layer and have a same layer and a same material as each other, as called for in claim 10 (claim 11 depends from claim 10);
wherein the first semiconductor layer and the second semiconductor layer directly contact the first buffer layer, as called for in claim 14;
a capacitor having a first capacitor electrode and a second capacitor electrode on the first capacitor electrode, wherein the first capacitor electrode is between the first gate electrode in the non-display area and the second gate electrode in the display area from a plan view, as called for in claim 15 (claims 16, 18, and 19 depend from claim 15).
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JORDAN M KLEIN whose telephone number is (571)270-7544. The examiner can normally be reached 9:00 am - 5:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/J.M.K/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
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