DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
IDS
The IDS document(s) filed on June 21, 2024 has been considered. Copies of the PTO-1449 documents are herewith enclosed with this office action.
Specifications
The title is objected to because a more descriptive title is requested.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the third insulating film, third opening, and second redistribution layer from claim 5 must be shown or the feature(s) canceled from the claim(s). Applicant appears to be combining the FIG. 4 embodiment of parent claim 2 and FIG. 5 embodiment of claim 5, but no such drawing corresponds to this mix of embodiments. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections – 35 U.S.C. § 112(b)
The following is a quotation of 35 U.S.C. § 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 2, 5, 6, and 8 are rejected under 35 U.S.C. § 112(b) or pre-AIA 35 U.S.C. § 112, second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant, regards as the invention.
As to claim 2, it is unclear what “between the collector electrode and the wiring and the first redistribution layer” is describing. The Examiner assumes the Applicant intends “between the collector electrode and the wiring” and “between the collector electrode and the first redistribution layer”.
Indication of Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter: claims 1, 3, 4, and 7 are indicated as being allowable because prior art fails to teach “wherein a width of the first opening of the first insulating film in a second direction parallel to the semiconductor substrate is larger than a width of the second opening of the second insulating film in the second direction” as recited in claim 1.
As to claim 1, Kurokawa et al. (U.S. Patent Publication No. 2019/0267479 A1), hereafter “Kurokawa”, is the closest prior art. Kurokawa teaches:
A semiconductor substrate 31. See Kurokawa, FIG. 16.
At least one transistor (semiconductor element 3 includes two bipolar transistors) on the semiconductor substrate and including a plurality of semiconductor layers. Id. at FIG. 2.
A wiring 46 on the transistor.
A first insulating film 42 including a first opening H2 in a region overlapping the transistor and the wiring in plan view in a first direction perpendicular to the semiconductor substrate. Kurokawa teaches the first insulating film 42 and first opening H2 overlapping the transistor and wiring in a cross-sectional view of FIG. 16 so they must also overlap in a plan view.
A first redistribution layer 54B on the first insulating film, overlapping the at least one transistor in the first direction in plan view, and electrically connected to the wiring via the first opening. Kurokawa teaches the first redistribution layer 54B overlapping the at least one transistor in a cross-sectional view of FIG. 16 so they must also overlap in a plan view. Kurokawa teaches the first redistribution layer 54B electrically connected to the wiring 46 via the first stress-relieving layer 51C, which is formed from electrically conductive metals such as titanium or tungsten. Id. at ¶ [0047].
A second insulating film 26 covering the first redistribution layer and the first insulating film, and including a second opening H16 in a region overlapping at least a part of the first redistribution layer in the first direction in plan view. Kurokawa teaches the second opening in a region overlapping at least a part of the first redistribution layer in a cross-sectional view of FIG. 16 so they must also overlap in a plan view.
A bump 39 electrically connected to the first redistribution layer via the second opening.
However, Kurokawa does not teach teach “wherein a width of the first opening of the first insulating film in a second direction parallel to the semiconductor substrate is larger than a width of the second opening of the second insulating film in the second direction” because a width of the first opening H2 is clearly less, not larger than, a width of the second opening H16. Even if the first insulating film were instead mapped to 26 so that the first opening is instead H16, then Kurokawa would not teach subsequent limitations such as “a second insulating film covering the first redistribution layer and the first insulating film” etc..
No other prior art was found.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUBERR CHI whose telephone number is (571)270-3955. The examiner can normally be reached 10am to 6pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SUBERR L CHI/Primary Examiner, Art Unit 2893
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