DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to 02/03/2026 Amendment.
Claims 21-32, 36-37, 40 are pending and examined. Claims 33-35, 38-39 have been cancelled.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 21-22, 24-25, 30 are rejected under 35 U.S.C. 103 as being unpatentable over US 8,982,636 to Chou et al. (hereafter Chou) in view of US 4,807,188 to Casagrande (hereafter Casagrande) with support from US 7,417,898 to Mori (hereafter Mori).
Regarding independent claim 21, Chou teaches a semiconductor device, comprising:
an array of memory cells, wherein each memory cell includes a transistor operable to represent FIG. 2: memory array 12 and memory cell MC having bits B1 and B2); and
control-circuitry coupled to the array of memory cells, configured to determine second binary bit values stored therein,
sense the first binary bit value based on a comparison between a first current and a reference current (sensing and determining threshold voltage of first bit in steps (a) and (b) of FIG. 5);
sense the second binary bit value based on a comparison between a second current and the reference current (sensing and determining threshold voltage of second bit in step (a) of FIG. 5 and step (b’) of FIG. 6);
obtain a delta cell current from the first and second currents (FIG. 5: step (c));
determine one of the logic states of the each memory cell based on a comparison between the delta cell current and the reference current.
Chou teaches obtaining the delta current instead of average cell current. Chou also does not teach strikethrough limitations.
Casagrande teaches a semidouble cell operable to represent one singular logic state based on at least two binary bit values stored independently therein (see FIG. 1); inherent control-circuitry coupled to the array of memory cells, configured to determine the singular logic state of the semidouble memory cell based at least partly on both first and second binary bit values stored therein, wherein the first and second binary bit values comprise a same stored value (see 2-60-3:7).
Since Chou and Casagrande are all from the same field of endeavor, the purpose disclosed by Casagrande would have been recognized in the pertinent art of Chou.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to:
store same logic in different storage locations as suggested in Casagrande to the memory cell of Chou for redundancy purpose when the memory cell has high programming and erasing cycles (see Casagrande, 1:7-66). It is similar to data states “00” and “11” stored in dual-bit memory cell of Mori (see FIG. 2, and 8:53-67).
it is a common approach to obtain average/mean cell current instead of delta cell current between currents of same logic state because the delta cell current may not significant for comparison to a reference current.
Regarding dependent claim 22, Chou teaches wherein the first current is greater than the reference current (FIG. 5: YES result from step (b)), the delta current cell current is generated based on both the first and the second current (FIG. 5: step (c)).
Regarding dependent claim 24, Chou teaches a control-circuitry comprises a processor operable to: sense and store the first current; sense and store the second current; generate the average cell current based on the first and second currents; and compare the average cell current to the reference current to determine a logic state of the each memory cell (FIG. 2: operation circuits 14 and 16).
Regarding dependent claim 25, Chou teaches wherein: the first current corresponds to charge trapped in a first bit location in a shared charge trapping layer in the each memory cell; the second current corresponds to charge trapped in a second bit location in the shared charge trapping layer in the each memory cell, wherein the first and second bit locations are physically separated from one another (see FIG. 9).
Regarding dependent claim 30, Chou teaches wherein: the first current corresponds to charge trapped in a first bit location in the each memory cell; the second current corresponds to charge trapped in a second bit location in the each memory cell, wherein the first and second bit locations are physically separated from one another (see FIG. 9).
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Chou in view of Casagrande in view of Mori in view of US 8,686,341 to Noiret et al. (hereafter Noiret).
Chou and Casagrande teach, as applied in prior rejection of claim 21, all claimed subject matter except further limitations set forth in the following claim(s).
Regarding dependent claim 23, Noiret teaches the control-circuitry comprises: a current-to-voltage (1-V) converter operable to convert the first current to a first voltage (FIG. 1: switch Ks and capacitor Cs), and a second current to a second voltage (FIG. 1: switch Kr and capacitor Cr); a number of capacitors coupled to the 1-V converter including at least a first capacitor operable to store the first voltage and a second capacitor operable to store the second voltage (FIG. 1: capacitors Cs and Cr, respectively).
Mori teaches an averaging circuit operable to output an average cell voltage based on the first voltage and the second voltage (FIG. 1: averaging circuit 104); and a comparator coupled to the averaging circuit operable to compare the average cell voltage to a reference voltage to determine the one singular logic state of the each memory cell (FIG. 21: read/verification circuit 614).
Since Chou, Casagrande, Mori, and Noiret are all from the same field of endeavor, the purpose disclosed by Noiret would have been recognized in the pertinent art of Chou/Casagrande/Mori.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to realize that capacitors are well-known in converting a cell current to voltage for voltage comparison in reading memory cell(s).
Claims 26-27, 29 are rejected under 35 U.S.C. 103 as being unpatentable over Chou in view of US 10,366,758 to Kurafugi et al. (hereafter Kurafugi) with support from Mori.
Regarding independent claim 26, Chou teaches a semiconductor device, comprising:
an array of memory cells, wherein each memory cell includes a transistor operable to represent FIG. 2: memory array 12 and memory cell MC having bits B1 and B2); and
control-circuitry coupled to the array of memory cells, configured to determine
sense the first binary bit value based on a first current (sensing and determining threshold voltage of first bit in steps (a) and (b) of FIG. 5);
sense the second binary bit value based on a second current (sensing and determining threshold voltage of second bit in step (a) of FIG. 5 and step (b’) of FIG. 6);
compare the first and second currents to generate a difference cell current (FIG. 5: step (c));
determine one of the logic states of the each memory cell based on the difference cell current.
Chou also does not teach strikethrough limitations.
Kurafugi teaches a pair of memory cells operable to represent one singular logic state based on at least two binary bit values stored independently therein (FIG. 1: e.g. memory cells M1a and M1b); control-circuitry coupled to the array of memory cells, configured to determine the singular logic state of the pair of memory cells based at least partly on both first and second binary bit values stored therein, wherein the first and second binary bit values are complementary (see Abstract).
Since Chou and Kurafugi are all from the same field of endeavor, the purpose disclosed by Kurafugi would have been recognized in the pertinent art of Chou.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to store complementary logic states in different storage locations as suggested in Kurafugi to the memory cell of Chou for reliability when the memory cells has high programming and erasing cycles. It is similar to data states “01” and “10” stored in dual-bit memory cell of Mori (see FIG. 2, and 8:53-67).
Regarding dependent claim 27, Kurafugi teaches wherein the singular logic state of the each memory cell is determined without use of a reference current (FIG. 4: because the two currents of the two memory cells are compared with each other).
Regarding dependent claim 29, Chou teaches wherein the control-circuitry comprises a processor operable to: sense and store the first current; sense and store the second current; compare the first current to the second current to obtain the difference cell current; and determine the singular logic state of the each memory cell based on the magnitude of the difference cell current (FIG. 2: operation circuits 14 and 16).
Claim 28 is rejected under 35 U.S.C. 103 as being unpatentable over Chou in view of Kurafugi in view of Noiret.
Chou and Kurafugi teach, as applied in prior rejection of claim 21, all claimed subject matter except some limitations.
Regarding dependent claim 28, Noiret teaches the control-circuitry comprises: a current-to-voltage (1-V) converter operable to convert the first current to a first voltage (FIG. 1: switch Ks and capacitor Cs), and a second current to a second voltage (FIG. 1: switch Kr and capacitor Cr); a number of capacitors coupled to the 1-V converter including at least a first capacitor operable to store the first voltage and a second capacitor operable to store the second voltage (FIG. 1: capacitors Cs and Cr, respectively).
Kurafugi further teaches a comparator operable to compare the first voltage and the second voltage, and to determine the singular logic state of the each memory cell based on the difference between the first voltage and the second voltage (FIG. 4: SA1).
Since Chou, Kurafugi and Noiret are all from the same field of endeavor, the purpose disclosed by Noiret would have been recognized in the pertinent art of Chou/ Kurafugi.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to realize that capacitors are well-known in converting a cell current to voltage for voltage comparison in reading memory cell(s).
Allowable Subject Matter
Claims 31-32, 36-37, 40 are allowed.
Response to Arguments
Applicant's arguments filed 02/03/2026 have been fully considered but they are not persuasive.
Applicant argues:
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Examiner respectfully disagrees with these arguments. Examiner has not used Applicant’s specification as a road map for the proposed combined as Applicant alleges. “Average/mean current” from variation of current values has been widely used in memory technology in order to cover a possible range. Examiner provides Naveh et al. (US 10,984,861) as an example to support Examiner’s statement. Naveh describes, in FIG. 9 and 8:22-29, an averaging or summing circuit 924 can generate a reference resistance Rref that is an average of the received reference resistances (Rref0 to Rrefn) of reference cells 904 programmed to a same state.
Applicant further argues:
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Examiner respectfully disagrees with these arguments. Examiner kindly directs Applicant to Chou, FIG. 3B and 3:21-44, which describes:
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The highlighted text clearly describes the memory cell is able to be programmed two logic values 1 and 0, wherein logic values 1 and 0 are seen complementary states.
Claims 21-32, 36-37, 40 maintain rejected for the reasons set forth above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VANTHU NGUYEN whose telephone number is (571)272-1881. The examiner can normally be reached M-F: 7:00AM - 3:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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May 8, 2026
/VANTHU T NGUYEN/Primary Examiner, Art Unit 2824
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