DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to the communications dated 02/03/2025.
Claims 1-25 are pending in this application.
Acknowledges
2. Receipt is acknowledged of the following items from the Applicant.
Information Disclosure Statements (IDS) filed on 06/21/2024, and 02/03/2025. The references cited on the PTOL 1449 form have been considered.
Applicant is requested to cite any relevant prior art if being aware on form PTO-1449 in accordance with the guidelines set for in M.P.E.P. 609.
Foreign Priority
3. Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been placed of record in the file.
Specification
4. The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 U.S.C. § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claims 1-4, 12-17, 20-21, and 23-24 are rejected under 35 U.S.C. 103 as being unpatentable over Wahl (US 2009/0026542) in view of Renaud et al. (US 2023/0124686)
Regarding claim 1, Wahl discloses a high voltage semiconductor device, comprising:
a substrate 112 (see Fig. 2A) having a background doping of a first conductivity type (n-type) and comprising doped shielding regions 264, 268 of a complementary second conductivity type formed along a first substrate surface;
an insulator layer 114 formed on the first substrate surface;
a semiconductor layer 116 formed on the insulator layer 114 opposite to the substrate 112;
a first interlayer dielectric 119 formed on the semiconductor layer 116;
a first metal layer 266 comprising laterally separated first field plate elements 266 formed on first portions of the first interlayer dielectric 119 in a termination region.
Wahl fails to disclose:
a second interlayer dielectric formed on the first metal layer and on second portions of the first interlayer dielectric between the first field plate elements.
Renaud discloses:
A high voltage semiconductor device, shown in Figs. 1-2, comprising:
a first interlayer dielectric 130 formed on a semiconductor layer 106/108;
a first metal layer 160 comprising a field plate element 160 formed on first portions of the first interlayer dielectric 130 in a termination region, and
a second interlayer dielectric 170 formed on the first metal layer 160 and on second portions of the first interlayer dielectric 130 surrounding and covering the first field plate element 160.
It would have been obvious to one of ordinary skills in the art at the time the invention was made to modify the invention of Wahl to further comprise a second interlayer dielectric surrounding and covering the field plate element(s), as that taught by Renaud, in order to provide protection to the field plate elements, thereby to increase the performance of the device.
Regarding claim 2, Wahl/Renaud discloses the high voltage semiconductor device of claim 1, wherein the first field plate elements 266 laterally surround a first device region. See Fig. 2A of Wahl.
Regarding claim 3, Wahl/Renaud discloses the high voltage semiconductor device of claim 1, wherein a top surface of the second interlayer dielectric 170 opposite the first metal layer is planar (at least on the right side of the field plate 160), and wherein the second interlayer dielectric comprises openings 174 extending from the top surface. See Figs. 1-2 of Renaud.
Regarding claim 4, Wahl/Renaud discloses the high voltage semiconductor device of claim 1, further comprising: an uppermost metal layer 280, 185/186 formed on the second interlayer dielectric 170. See Fig. 2 of Renaud.
Regarding claim 12, Wahl/Renaud discloses the high voltage semiconductor device of claim 4, wherein the uppermost metal layer is formed directly on the second interlayer dielectric 170. See Fig. 2 of Renaud.
Regarding claim 13, Wahl/Renaud discloses the high voltage semiconductor device of claim 4, further comprising: at least one intermediate metal layer (filling opening 278 inf Fig. 2) formed between (and connecting) the first metal layer and the uppermost metal layer. See Fig. 2, and para. 0068 of Renaud.
Regarding claim 14, Wahl/Renaud discloses the high voltage semiconductor device of claim 13, wherein each of the at least one intermediate metal layer comprises intermediate field plate elements, and wherein each intermediate field plate element is electrically connected with one of the first field plate elements (via opening 278). See Fig. 2 and para. 0068 of Renaud.
Regarding claim 15, Wahl/Renaud discloses the high voltage semiconductor device of claim 4, comprising all claimed limitations, as discussed above, except for wherein a thickness of the uppermost metal layer is at least 1.2-fold a thickness of the first metal layer.
However, it has been held that where the only difference between the prior art and the claims was a recitation of relative dimensions/thickness of the claimed element, and a device having the claimed relative dimensions/thickness would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device (MPEP §2144.04). It would have been obvious that a mere change in size/thickness of a component is generally recognized as being within the level of ordinary skill in the art.
It is to be expected that a change in size, thickness would be an unpatentable modification.
Under some circumstances, however, changes such as these may impart patentability to a process if the particular ranges claimed produce a new and unexpected result which is different in kind and not merely degree from the results of the prior art...such ranges are termed "critical ranges and the applicant has the burden of proving such criticality. See In re Aller, 220 F.2d 454, 105 USPQ 233,235 (CCPA 1955).
The instant specification contains no disclosure of either the critical nature of the claimed dimensions/thickness or of any unexpected results arising therefrom. Where patentability is aid to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. (.In re Woodruff, 919 F.2d 1575, 1578 (Fed. Cir. 1990).)
The claimed limitation regarding to the thickness of the uppermost metal layer do/does not bear any critical point that would establish patentability, and is/are not sufficient to patentable distinguish over the prior art, therefore being considered as unpatentable limitation(s) because it would have involve only a mere change in size/thickness of a component. A change in size/shape is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). See MPEP §2144.04).
Regarding claim 16, Wahl/Renaud discloses the high voltage semiconductor device of claim 1, wherein the doped shielding regions 265-268 form laterally separated frames around a first device region. See Fig. 2A of Wahl.
Regarding claim 17, Wah;/Renaud discloses the high voltage semiconductor device of claim 1, further comprising: an active element (comprising gates G) formed in a transition device portion 162’ of the semiconductor layer, wherein the transition device portion extends from a first device region 210 on a first side of the first field plate elements 266 into a second device region 220 on a second side of the first field plate elements 266. See Fig. 2A of Wahl.
Regarding claim 20, Wahl/Renaud discloses the high voltage semiconductor device of claim 17, wherein the active element is a bootstrap diode. See Fig. 2A of Wahl.
Regarding claim 21, Wahl/Renaud discloses the high voltage semiconductor device of claim 17, wherein the active element is a level shift transistor. See Fig. 2A of Wahl.
Regarding claim 23, Wahl/Renaud discloses the high voltage semiconductor device of claim 17, wherein the active element comprises a compensation structure 268-112-264 (Fig. 2A of Walh), and wherein the compensation structure comprises p doped regions and n doped regions alternatingly arranged along a horizontal direction orthogonal to a current flow direction in the active element.
Regarding claim 24, Wahl/Renaud discloses the0 high voltage semiconductor device comprising all claimed limitations. See the rejection of claim 15.
Allowable Subject Matter
7. Claims 5-11, 18-19, and 22 allowable.
Claims 5-11, 18-19, and 22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest the claimed high voltage semiconductor device (in addition to the other limitations in the claim) comprising:
Claims 5-11:
wherein the uppermost metal layer comprises laterally separated second field plate elements, and wherein the second interlayer dielectric vertically separates the second field plate elements from the first field plate elements.
Claims 18-19:
wherein the shielding regions form laterally separated frames around a first device region, and wherein modified sections of the shielding regions facing the transition device portion differ from second sections in width and/or dopant concentration.
Claim 22:
a further active element with different functionality than the active element, wherein the first field plate elements laterally overlap both active elements in a respective overlap area, the first field plate elements having a same spacing among each other in both overlap areas.
Allowance / Reasons for Allowance
8. Claim 25 is allowed.
The following is an examiner’s statement of reason for allowance:
None of the references of record teaches or suggests the claimed high voltage semiconductor device (in combination set forth in the claim) comprising:
wherein the uppermost metal layer comprises laterally separated second field plate elements,
wherein the second interlayer dielectric vertically separates the second field plate elements from the first field plate elements,
wherein a lateral gap is formed between adjacent ones of the second field plate elements,
wherein at least 50% of a lateral extension of the lateral gap is laterally overlapped by one of the first field plate elements.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance”.
Conclusion
9. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the day of this letter. Failure to respond within the period for response will cause the application to become abandoned (see M.P.E.P 710.02(b)).
A shortened time for reply may be extended up to the maximum six-month period (35 U.S.C. 133). An extension of time fee is normally required to be paid if the reply period is extended. The amount of the fee is dependent upon the length of the extension. Extensions of time are generally not available after an application has been allowed.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Dao H. Nguyen whose telephone number is (571)272-1791. The examiner can normally be reached on Monday-Friday, 9:00 AM – 5:00 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke, can be reached on (571)272-1657. The fax numbers for all communication(s) is 571-273-8300.
Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-1633.
/DAO H NGUYEN/Primary Examiner, Art Unit 2818 September 2, 2026
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