DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
However, should applicant desire to obtain the benefit of foreign priority under 35
U.S.C. 119(a)-(d) prior to declaration of an interference, a certified English translation of
the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and
41.202(e).
Failure to provide a certified translation may result in no benefit being accorded
for the non-English application.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-3 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 2, Claim 2 recites the limitation "the recess" in line 1. There is insufficient antecedent basis for this limitation in the claim.
The only recesses that have been previously introduced are “a plurality of recesses” in Claim 1. As written, it is unclear whether “the recess” in Claim 2 is referring to the totality of the plurality of recesses, a specific recess previously unintroduced, or some other element.
For examination purposes, Claim 2 has been interpreted as follows, based on context, FIGs. 2A-2B, and paragraphs [0013, 0023, 0053]:
Claim 2: The electronic package of claim 1, wherein a plurality of detachable blocks [[is]] are formed in the plurality of recesses.
Regarding Claim 3, Claim 3 depends from Claim 2 and does not resolve the indefiniteness; therefore, it is rejected for the same reasons as Claim 2 due to its dependence therefrom. For clarity, consistency, and examination purposes, Claim 3 has been interpreted as follows:
Claim 3: The electronic package of claim 2, wherein the plurality of detachable blocks includes polyimide material or polyoxadiazole benzene material.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 4-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ng et al., US PGPub 2020/0402965 A1 (hereinafter referred to as “Ng”).
Regarding Claim 1, Ng discloses an electronic package (FIGs. 2A-2H; [0012]), comprising:
an encapsulating layer having a first surface and a second surface opposing to each other (FIG. 2C, encapsulation layer 25, first surface 25a, second surface 25b; [0032]),
wherein a plurality of recesses are formed on the first surface (see annotated FIG. 2C below, with a plurality of recess on the first surface 25a indicated with the red dashed boxes. Specifically, Ng clearly has recesses formed in the first surface 25a of the encapsulation layer 25 whereby the first electronic component 21 and conductive pillars 23 are exposed from the recesses; that the recesses are filled is irrelevant and is still interpreted to read on the claimed limitation as written);
a first electronic component embedded in the encapsulating layer and exposed from some of the plurality of recesses (see annotated FIG. 2C below, first electronic component 21, encapsulation layer 25, at least the top surface of the first electronic component 21 is exposed from the recess in which it sits, indicated by the red solid arrow; [0032]);
and a plurality of conductive pillars embedded in the encapsulating layer and exposed from some of the plurality of recesses (see annotated FIG. 2C below, conductive pillars 23 in encapsulation layer 25, at least the top surface of the conductive pillars 23 exposed from the recess in which it sits, indicated by the purple solid arrow; [0032]).
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Regarding Claim 4, Ng further discloses the electronic package of claim 1, as discussed above.
Ng further discloses further comprising a circuit portion formed on the first surface and in the plurality of recesses (FIG. 2D, circuit structure 20, plurality of insulation layers 200, plurality of redistribution layers (RDLs) 201; [0036-0037]), wherein the circuit portion is electrically connected to the plurality of conductive pillars and the first electronic component ([0038] RDLs are made of copper, for example, which obviously provides the ability to conduct electricity due to the inherent property of metals and being in direct contact with the conductive pillars 23 and conductive bodies 22 of the first electronic component 21).
Regarding Claim 5, Ng further discloses the electronic package of claim 4, as discussed above.
Ng further discloses wherein the circuit portion includes a dielectric layer formed on the first surface and a circuit body embedded in the dielectric layer and extending into the plurality of recesses (see annotated FIG. 2D below, plurality of insulation layers 200 on first surface 25a of the encapsulation layer 25, RDLs 201 embedded between insulation layers 200, and extending into the plurality of recesses as indicated by red solid arrow where, as above in FIG. 2C, recesses are indicated by red dashed box annotations; [0037]).
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Regarding Claim 6, Ng further discloses the electronic package of claim 5, as discussed above.
Ng further discloses wherein the circuit body is electrically connected to the plurality of conductive pillars and the first electronic component ([0038] RDLs are made of copper, for example, which obviously provides the ability to conduct electricity due to the inherent property of metals and being in direct contact with the conductive pillars 23 and conductive bodies 22 of the first electronic component 21).
Regarding Claim 7, Ng further discloses the electronic package of claim 4, as discussed above.
Ng further discloses further comprising a circuit structure formed on the circuit portion, such that the circuit structure is electrically connected to the circuit portion (FIG. 2D, circuit structure 20, conductive pad 202; [0037]).
Regarding Claim 8, Ng further discloses the electronic package of claim 7, as discussed above.
Ng further discloses further comprising a second electronic component disposed on the circuit structure (FIG. 2E, second electronic component 26 on the circuit structure 20, specifically on the conductive pad 202; [0037-0039]).
Regarding Claim 9, Ng further discloses the electronic package of claim 1, as discussed above.
Ng further discloses wherein a passivation layer is bonded to the second surface of the encapsulating layer (FIG. 2C, insulation layer 91 on second surface 25b of the encapsulation layer 25; [0028]).
Regarding Claim 10, Ng further discloses the electronic package of claim 9, as discussed above.
Ng further discloses further comprising a wiring layer formed on the passivation layer, wherein the wiring layer is electrically connected to the plurality of conductive pillars (FIG. 2G, circuit portion 240 on insulation 91 and electrically connected to conductive pillars 23; [0046-0049]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2-3 and 11-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ng in view of Lin et al., US PGPub 2019/0103362 A1 (hereinafter referred to as “Lin”).
Regarding Claim 2, Ng discloses the electronic package of claim 1, as discussed above.
Ng is silent on wherein a detachable block is formed in the recess.
However, Lin, which is similarly directed to electronic packaging and the manufacturing method thereof, in particular, for example, integrated Fan-Out packages, does teach the use of sacrificial structures for forming recesses in the encapsulating material. Specifically, Lin teaches sacrificial/polymer dots can be removed to form recesses in conductive pillars embedded in an encapsulation layer, thereby acting as detachable blocks formed in the recess (the same recess in which the metal posts 36 are formed—see Lin FIG. 5B).
Lin further teaches that the use and removal of these sacrificial/polymer dots results in the formation of recesses in the encapsulation layer and metal posts and thereafter having some portions of the circuit layer (e.g., solder regions) formed in those recesses, which is beneficial in allowing for increased control over total thickness of the package (e.g., keeping the total thickness of the package the same even while increasing heat dissipation) (Lin FIGs. 15-16 and paragraphs [0021, 0045-0046, 0048, 0068]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the electronic package of Ng with the teachings of Lin to form sacrificial/polymer dots in the recess(es), such that wherein a detachable block is formed in the recess for the benefit of allowing solder regions, for example, to be formed in such recesses upon removal of the sacrificial/polymer dots and thereby keeping the total thickness of the package the same even while increasing heat dissipation (Lin paragraph [0068]).
Regarding Claim 3, Ng in view of Lin discloses the electronic package of claim 2, as discussed above.
Lin further discloses wherein the detachable block includes polyimide material or polyoxadiazole benzene material (FIGs. 15-16; [0021]).
Regarding Claim 11, Ng discloses a manufacturing method of an electronic package, comprising (FIGs. 2A-2H; [0012]):
disposing a plurality of conductive pillars and a first electronic component on a carrier board (FIG. 2A, conductive pillars 23, first electronic component 21, carrier board 9; [0027]),
forming an encapsulating layer on the carrier board, so that the encapsulating layer covers the first electronic component, and the plurality of conductive pillars (FIG. 2C, encapsulation layer 25, carrying board 9, first electronic component 21, conductive pillars 23; [0032]),
wherein the encapsulating layer has a first surface and a second surface opposing to each other, such that the second surface of the encapsulating layer is bonded to the carrier board, (FIG. 2C, encapsulation layer 25, first surface 25a, second surface 25b, carrying board 9; [0032]);
Ng does not disclose or explicitly teach the use of a detachable block for the purpose of forming recesses, such as wherein a plurality of detachable blocks are formed on end surfaces of the plurality of conductive pillars and the first electronic component;
[so that the encapsulating layer covers] the plurality of detachable blocks,
and that the plurality of detachable blocks are exposed from the first surface of the encapsulating layer
and removing the plurality of detachable blocks to form a plurality of recesses on the first surface of the encapsulating layer, so that the plurality of conductive pillars and the first electronic component are exposed from the plurality of recesses.
However, Lin, which is similarly directed to electronic packaging and the manufacturing method thereof, for example, integrated Fan-Out packages, does teach the use of sacrificial structures for forming recesses in the encapsulating material. Specifically, Lin teaches sacrificial/polymer dots on conductive pillars can be removed to form recesses in the conductive pillars and thereby the encapsulation layer in which the pillars are embedded.
The sacrificial/polymer dots 24 are formed on what would be equivalent to the second surface of the encapsulating layer (see Lin FIGs. 5B, 6B, 15-16 and paragraphs [0032, 0045]); however, it would be obvious to one of ordinary skill in the art that Lin does not explicitly teach that the sacrificial/polymer dots need only be on or in such a configuration. Indeed, it would have been an obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that swapping the position of the sacrificial/polymer dots from one end of the conductive pillars to the other would result in the same known, and predictable, purpose and benefit of forming a recess upon removal and thereby allowing electrical connections in the formed recesses.
Lin further teaches that the use and removal of these sacrificial/polymer dots results in the formation of recesses, and thereafter having some portions of the circuit layer (e.g., solder regions) formed in those recesses, is beneficial in allowing for increased control over total thickness of the package (e.g., keeping the total thickness of the package the same even while increasing heat dissipation) (Lin FIGs. 15-16 and paragraphs [0021, 0045-0046, 0048, 0068]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Ng with the teachings of Lin to use sacrificial/polymer dots as detachable blocks for forming recesses on the surface of the encapsulating layer, exposing the conductive pillars and first electronic component, for the benefit of allowing solder regions, for example, to be formed in such recesses and thereby keeping the total thickness of the package the same even while increasing heat dissipation (Lin paragraph [0068]). That is, the modified method of Ng in view of Lin therefore discloses wherein a plurality of detachable blocks are formed on end surfaces of the plurality of conductive pillars and the first electronic component (Lin FIGs. 5B, 6B, 15-16, sacrificial/polymer dots 24, recesses 79, [0021, 0045-0046, 0048]; Ng FIG. 2C, end surface 23a of the conductive pillars 23, first electronic component 21, [0032]);
[so that the encapsulating layer covers] the plurality of detachable blocks (Lin FIGs. 5B, 6B, 15-16),
and that the plurality of detachable blocks are exposed from the first surface of the encapsulating layer (Lin FIGs. 15-16 in combination with Ng FIG. 2C wherein the conductive pillars 23 are exposed from the first surface 25a of the encapsulation layer 25 and therefore, so too would the sacrificial/polymer dots 24 of Lin be exposed),
and removing the plurality of detachable blocks to form a plurality of recesses on the first surface of the encapsulating layer, so that the plurality of conductive pillars and the first electronic component are exposed from the plurality of recesses (Lin FIGs. 15-16, sacrificial/polymer dots 24 removed to form recess 79, [0045-0046] in combination with Ng FIG. 2C conductive pillars 23, first electronic component 21).
Regarding Claim 12, Ng in view of Lin (Ng/Lin) discloses the manufacturing method of claim 11, as discussed above.
Lin further discloses wherein the detachable block includes polyimide material or polyoxadiazole benzene material (FIGs. 15-16; [0021]).
Regarding Claim 13, Ng/Lin discloses the manufacturing method of claim 11, as discussed above.
Ng further discloses further comprising forming a circuit portion on the first surface of the encapsulating layer and in the plurality of recesses (FIG. 2D, circuit structure 20, plurality of insulation layers 200, plurality of redistribution layers (RDLs) 201; [0036-0037]), so that the circuit portion is electrically connected to the plurality of conductive pillars and the first electronic component ([0038] RDLs are made of copper, for example, which obviously provides the ability to conduct electricity due to the inherent property of metals and being in direct contact with the conductive pillars 23 and conductive bodies 22 of the first electronic component 21).
Regarding Claim 14, Ng/Lin discloses the manufacturing method of claim 13, as discussed above.
Ng further discloses wherein the circuit portion includes a dielectric layer formed on the first surface and a circuit body embedded in the dielectric layer and extending into the plurality of recesses (FIG. 2D, plurality of insulation layers 200 on first surface 25a of the encapsulation layer 25, RDLs 201 embedded between insulation layers 201; [0037]).
Regarding Claim 15, Ng/Lin discloses the manufacturing method of claim 14, as discussed above.
Ng further discloses wherein the circuit body is electrically connected to the plurality of conductive pillars and the first electronic component ([0038] RDLs are made of copper, for example, which obviously provides the ability to conduct electricity due to the inherent property of metals and being in direct contact with the conductive pillars 23 and conductive bodies 22 of the first electronic component 21).
Regarding Claim 16, Ng/Lin discloses the manufacturing method of claim 13, as discussed above.
Ng further discloses further comprising forming a circuit structure on the circuit portion, such that the circuit structure is electrically connected to the circuit portion (FIG. 2D, circuit structure 20, conductive pad 202; [0037]).
Regarding Claim 17, Ng/Lin discloses the manufacturing method of claim 16, as discussed above.
Ng further discloses further comprising disposing a second electronic component on the circuit structure (FIG. 2E, second electronic component 26 on the circuit structure 20, specifically on conductive pad 202; [0037-0039]).
Regarding Claim 18, Ng/Lin discloses the manufacturing method of claim 11, as discussed above.
Ng further discloses wherein the carrier board has a passivation layer to be bonded to the second surface of the encapsulating layer, the plurality of conductive pillars and the first electronic component (FIG 2C, insulation layer 91 on carrier board 9 and thereby conductive pillars 23 and first electronic component 21; [0044-0045]).
Regarding Claim 19, Ng/Lin discloses the manufacturing method of claim 18, as discussed above.
Ng further discloses further comprising removing the carrier board (FIGs. 2E-2F, carrier board 9; [0044-0045]).
Regarding Claim 20, Ng/Lin discloses the manufacturing method of claim 19, as discussed above.
Ng further discloses further comprising forming a wiring layer on the passivation layer, wherein the wiring layer is electrically connected to the plurality of conductive pillars (FIG. 2G, circuit portion 240 on insulation layers 91 and electrically connected to conductive pillars 23; [0046-0049]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Ho et al., US PGPub 2020/0350285 A1, which is directed to an electronic package of similar structure, particularly with a plurality of conductive bodies serving a similar purpose as those in the main thrust of the claimed invention, but only providing the improved mechanical and electrical support to the semiconductor component and not also the conductive pillars in the encapsulation layer.
Tsai et al., US PGPub 2021/0098386 A1, which is directed to a similar electronic package structure and manufacturing method, with a conductive material serving a similar structure purpose as the circuit body in the claimed invention, but not explicitly formed through sacrificial layers and related processes.
Lee et al., US PGPub 2019/0172781 A1, which is directed to a similar semiconductor package structure with recess in the encapsulating material and thereafter filled with conductive material for a similar structural and thermal benefit as the circuit body in the claimed invention but not explicitly formed through sacrificial processes, such as detachable blocks for forming recesses.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Austin T. Woodard whose telephone number is (571)270-1958. The examiner can normally be reached M-F, 8am to 5pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Austin T Woodard/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
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