Prosecution Insights
Last updated: October 04, 2026
Application No. 18/750,645

T-Gate FET Structure

Final Rejection §102§103
Filed
Jun 21, 2024
Examiner
KUSUMAKAR, KAREN M
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
pSemi Corporation
OA Round
2 (Final)
87%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
854 granted / 979 resolved
+19.2% vs TC avg
Moderate +10% lift
Without
With
+9.8%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 11m
Avg Prosecution
18 currently pending
Career history
984
Total Applications
across all art units

Statute-Specific Performance

§101
1.1%
-38.9% vs TC avg
§103
44.7%
+4.7% vs TC avg
§102
37.9%
-2.1% vs TC avg
§112
8.4%
-31.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 979 resolved cases

Office Action

§102 §103
Status of Claims As of the amendment filed 8/31/26, no claims have been added, claims 2, 9, and 15 have been canceled, and claims 2, 4, 6-8, 11-13, 17, 29, and 20 have been amended. Therefore, claims 1, 3-8, 10-14, and 16-20 remain pending, with claims 1, 8, and 13 being independent. Response to Arguments Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 6, 13, and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chanemougame (US 2018/0204927). As to claims 1 and 13, Chanemougame teaches a metal-oxide-semiconductor field-effect transistor (MOSFET, see annotated fig. 22 below) having an active layer (210, [0029]) and including: (a) a source region (212) formed within the active layer of the MOSFET ([0029]); (b) a drain region (212) formed within the active layer of the MOSFET ([0029]); (c) a body region (211) within the active layer (210) of the MOSFET between the source region and the drain region (212, [0029]); and (d) a T-shaped gate structure (260 and 295) overlying the body region (211), the gate structure having a source region side (left side) and a drain region side (right side) and positioned to influence current flow through the body region ([0029]), the T-shaped gate structure including: (1) a gate oxide layer (261) in contact with an active layer of the FET MOSFET ([0035]); (2) a first conductive layer (262) in contact with the gate oxide layer (261, [0035]); (3) a second conductive layer (lower part of 295) in contact with the first conductive layer (262, [0052]); (4) a conductive gate contact (upper part of 295) in contact with the second conductive layer (lower part of 295, [0052]); (5) first and second insulating side-spacers (278) bracketing the sides of the first and second conductive layers ([0049]); wherein at least the first conductive layer has a shorter length than the conductive gate contact and a higher etch rate than the second conductive layer ([0050] and [0056], the first conductive layer is polysilicon and the second conductive layer is a standard via metal); and wherein the second conductive layer has a shorter length than the conductive gate contact (see fig. 22 below). PNG media_image1.png 732 784 media_image1.png Greyscale As to claims 6 and 19, Chanemougame further teaches the first and second insulating side-spacers conform to sides of the first and second conductive layers (see fig. 22 above, spacers 278 are below the gate contact and conform to the conductive layers). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 3 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Chanemougame in view of Chan (US 2005/0073014). As to claims 3 and 16, Chanemougame teaches the first conductive layer comprises poly-Si ([0056]) does not teach the first conductive layer comprises poly-SiGE alloy. However, Chan teaches a gate conductor similar to Chanemougame’s first conductive layer that does comprise a poly-SiGE alloy ([0017]). Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to use the poly-SiGe gate layer of Chan so as to adjust etching or doping profiles to assist with subsequent deposition and/or etching processes. Claim(s) 5, 14, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Chanemougame. As to claims 5, 14, and 18, Chanemougame does not teach at least one of a halo region or lightly- doped drain region located in the body region between the source region and the body region and/or between the drain region and the body region or the conductive gate contact includes a silicide. However, forming a silicide on the gate contact would have been obvious so as to reduce interconnection resistance. Furthermore, forming halo/LDD regions are also known in the art and would have been obvious so as to adjust channel properties. Allowable Subject Matter Claims 8 and 10-12 are allowed and claims 4, 7, 17, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior art taken either singularly or in combination fails to anticipate or fairly suggest the limitations of the claims listed above in such a manner that a rejection under 35 U.S.C. 102 or 103 would be proper. The prior art fails to teach a combination of all of the features in the claims. As to claims 4 and 17, Chanemougame fails to teach the second conductive layer comprises polysilicon. The second conductive layer is specifically a metal contact ([0050]). As to claims 7 and 20, Chanemougame fails to teach air-gaps separating some or all of at least the first conductive layer from the first and second insulating side-spacers. Chanemougame teaches air gaps 271, however they are a part of the spacers and do not serve to separate the spacers from the conductive layer(s). As to claim 8, Chanemougame fails to teach a polysilicon second conductive layer in contact with a poly-SiGe first conductive layer. As stated above, the second conductive layer is very clearly a metal contact. The remaining claims are allowed at least because they depend from allowed claim 8. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action. Any response to this Office Action should be faxed to (571) 273-8300 or mailed to: Commissioner for Patents P.O. Box 1450 Alexandria, VA 22313-1450 Hand-Delivered responses should be brought to: Customer Service Window Randolph Building 401 Dulany Street Alexandria, VA 22313 Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAREN M KUSUMAKAR whose telephone number is (571)270-3520. The examiner can normally be reached on Monday – Friday from 7:30a – 4:30p EST. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached on 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KAREN KUSUMAKAR/ Primary Examiner, Art Unit 2897 9/12/26
Read full office action

Prosecution Timeline

Jun 21, 2024
Application Filed
Jun 22, 2026
Non-Final Rejection mailed — §102, §103
Aug 31, 2026
Response Filed
Sep 15, 2026
Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
87%
Grant Probability
97%
With Interview (+9.8%)
1y 11m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 979 resolved cases by this examiner. Grant probability derived from career allowance rate.

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