Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Election/Restriction
Applicant’s election of Group I, without traverse, is acknowledged.
Specification Objection
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections – 35 U.S.C. 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 5 recites the limitation "a capacitor structure". It is unclear whether the recited "a capacitor structure" was intended to relate back to the "a capacitor structure" recited in Claim 1 or to set forth an additional capacitor structure. For the purpose of examination, the Examiner interprets the "a capacitor structure " recited in Claim 5 as the capacitor structure.
Claim Rejections – 35 U.S.C. 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AlA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim 1 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Duan (U.S. Patent Pub. No. 2021/0384117).
Regarding Claim 1
FIG. 4 of Duan discloses a semiconductor device (20), comprising: a first semiconductor structure, comprising: a stack structure comprising a first dielectric layer (lower 106), a second dielectric layer (upper 106), and a stack sub-structure stacked along a first direction; and a plurality of capacitor structures (104) extending through the stack structure along the first direction, wherein a size of a portion of the capacitor structure located in the first dielectric layer along a second direction is greater than a size of a portion of the capacitor structure located in the second dielectric layer along the second direction; and the second direction is perpendicular to the first direction.
Claims 1, 10, 14 and 20 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Rhie (U.S. Patent Pub. No. 2015/0221718).
Regarding Claim 1
FIG. 1 of Rhie discloses a semiconductor device (1), comprising: a first semiconductor structure, comprising: a stack structure comprising a first dielectric layer (136), a second dielectric layer (126), and a stack sub-structure stacked along a first direction; and a plurality of capacitor structures (102/103) extending through the stack structure along the first direction, wherein a size of a portion (103) of the capacitor structure located in the first dielectric layer along a second direction is greater than a size of a portion (102) of the capacitor structure located in the second dielectric layer along the second direction; and the second direction is perpendicular to the first direction.
Regarding Claim 10
FIG. 1 of Rhie discloses a side of the portion of a capacitor structure located in the first dielectric layer (136) that is in contact with the second dielectric layer (126) is a plane.
Regarding Claim 14
FIG. 1 of Rhie discloses a second semiconductor structure (101), wherein the first semiconductor structure and the second semiconductor structure are stacked along the first direction, and the second semiconductor structure comprises a peripheral circuit.
Regarding Claim 20
FIG. 1 of Rhie discloses a semiconductor device (1), comprising: a first semiconductor structure, comprising: a stack structure comprising a first dielectric layer (136), a second dielectric layer (126), and a stack sub-structure stacked along a first direction; and a plurality of capacitor structures (102/103) extending through the stack structure along the first direction, wherein a size of a portion (103) of the capacitor structure located in the first dielectric layer along a second direction is greater than a size of a portion (102) of the capacitor structure located in the second dielectric layer along the second direction; and the second direction is perpendicular to the first direction; and a peripheral circuit (101) coupled to the semiconductor device and configured to control at least one operation of the semiconductor device.
Claim Rejections – 35 U.S.C. 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 1 rejected under 35 U.S.C. 103 as being unpatentable over Rhie (U.S. Patent Pub. No. 2015/0221718), in view of Hiroi (U.S. Patent Pub. No. 2013/0285203).
Regarding Claim 1
FIG. 1 of Rhie discloses a semiconductor device (1), comprising: a first semiconductor structure, comprising: a stack structure comprising a first dielectric layer (124), a second dielectric layer (126), and a stack sub-structure stacked along a first direction; and a plurality of capacitor structures (102/103) extending through the stack structure along the first direction.
Rhie is silent with respect to “a size of a portion of the capacitor structure located in the first dielectric layer along a second direction is greater than a size of a portion of the capacitor structure located in the second dielectric layer along the second direction; and the second direction is perpendicular to the first direction”.
FIG. 6 of Hiroi discloses a similar semiconductor device, wherein a size of a portion (wider portion defined by 32) of the capacitor structure located in the first dielectric layer (26c) along a second direction is greater than a size of a portion (within 29b) of the capacitor structure located in the second dielectric layer (29b) along the second direction; and the second direction is perpendicular to the first direction.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Rhie, as taught by Hiroi. The ordinary artisan would have been motivated to modify Rhie in the above manner for purpose of eliminating influence of moisture, chemical solution components, radicals, and other factors migrated to a non-memory area ([0006] of Hiroi).
Claims 2-6 and 11-13 rejected under 35 U.S.C. 103 as being unpatentable over Rhie and Hiroi, in view of Lee (U.S. Patent Pub. No. 2022/0139920).
Regarding Claim 2
Rhie as modified by Hiroi discloses Claim 1.
Rhie as modified by Hiroi is silent with respect to “a plurality of vertical gate transistors, wherein each of the vertical gate transistors is coupled to a corresponding one of the capacitor structures, and comprises a semiconductor pillar extending along the first direction and a gate structure in contact with at least part of a side of the semiconductor pillar”.
FIG. 2 of Lee discloses a similar semiconductor device, wherein the first semiconductor structure further comprises: a plurality of vertical gate transistors, wherein each of the vertical gate transistors is coupled to a corresponding one of the capacitor structures (235), and comprises a semiconductor pillar (204) extending along the first direction and a gate structure (212) in contact with at least part of a side of the semiconductor pillar.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Rhie, as taught by Lee. The ordinary artisan would have been motivated to modify Rhie in the above manner for purpose of improving the area efficiency ([0006] of Lee).
Regarding Claim 3
FIG. 2 of Lee discloses a distance between one of two semiconductor pillars adjacent to a first semiconductor pillar of a plurality of semiconductor pillars along the second direction and the first semiconductor pillar is a first distance, and a distance between the other one of the two semiconductor pillars and the first semiconductor pillar is a second distance; and the first distance is greater than the second distance.
Regarding Claim 4
FIG. 2 of Lee discloses the plurality of semiconductor pillars include a plurality of semiconductor pillar groups, and the semiconductor pillar (204) group comprises two semiconductor pillars arranged along the second direction; the gate structure is located between the two semiconductor pillars of the semiconductor pillar group, and a distance between the two semiconductor pillars of the semiconductor pillar group is the first distance; and the first semiconductor structure further comprises an isolation structure (207) located between adjacent ones of the semiconductor pillar groups along the second direction, and a distance between two adjacent ones of the semiconductor pillar groups along the second direction is the second distance.
Regarding Claim 5
FIG. 2 of Lee discloses the first semiconductor structure further comprises a first insulation layer (230), and the isolation structure comprises a second insulation layer (207); the first insulation layer is located between the two semiconductor pillars (204) of a semiconductor pillar group and is in contact with the capacitor structure; the second insulation layer is in contact with a capacitor structure. With respect to “an etching-selectivity ratio of a material of the first dielectric layer to a material of the first insulation layer is greater than 10:1; and an etching-selectivity ratio of the material of the first dielectric layer to a material of the second insulation layer is greater than 10:1”, said ratio is related to the manufacturing processes and costs. Therefore, said ratio is considered to be a result effective variable. The claim to a specific ratio therefore constitutes an optimization of ranges. In re Huang, 100 F.3d 135, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996). It would have been obvious to one of ordinary skill in the art at the time of the invention to use the parameters as claimed, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art (MPEP 2144.05).
Regarding Claim 6
The recitation “an etching-selectivity ratio of a material of the first dielectric layer to a material of the second dielectric layer is greater than 10:1”, said ratio is related to the manufacturing processes and costs. Therefore, said ratio is considered to be a result effective variable. The claim to a specific ratio therefore constitutes an optimization of ranges. In re Huang, 100 F.3d 135, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996). It would have been obvious to one of ordinary skill in the art at the time of the invention to use the parameters as claimed, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art (MPEP 2144.05).
Regarding Claim 11
FIG. 3 of Lee discloses the first semiconductor structure further comprises a plurality of contact structures (332) extending along the first direction; and one of two opposite ends of the semiconductor pillar along the first direction is in contact with the contact structure.
Regarding Claim 12
FIG. 3 of Lee discloses a contact structure comprises a first end face and a second end face that are opposite along the first direction; the capacitor structure comprises a third end face and a fourth end face that are opposite along the first direction; and at least part of the first end face is in contact with the third end face.
Regarding Claim 13
FIG. 3 of Lee discloses the first end face of at least some of the contact structures is in contact with both the third end face and the first dielectric layer (331).
Claims 7-9 and 20 rejected under 35 U.S.C. 103 as being unpatentable over Duan, in view of Zhao (U.S. Patent Pub. No. 2022/0059540).
Regarding Claim 7
Duan discloses Claim 1, wherein a capacitor structure of the plurality of capacitor structure comprises a first electrode plate (111), a dielectric layer (106 between 111 and 112), a second electrode plate (112) and a support structure (portion of 106 located in the stack sub-structure); the first electrode plate extends into the second dielectric layer and the first dielectric layer from the stack sub-structure along the first direction; the support structure is located in the stack sub-structure and extends along the first direction, and the first electrode plate surrounds the support structure; a portion of the second electrode plate surrounds the first conductive layer and the second conductive layer; the dielectric layer is located between the first electrode plate and the second electrode plate; and a size of a portion of the support structure and the first electrode plate located in the stack sub-structure along the second direction is greater than the size of the portion of the capacitor structure located in the second dielectric layer (102) along the second direction.
Duan is silent with respect to “the stack sub-structure comprises a first conductive layer, a first support layer, a second conductive layer and a second support layer stacked along the first direction”.
FIG. 1 of Zhao discloses a similar semiconductor device, wherein the stack sub-structure comprises a first conductive layer (33), a first support layer (32), a second conductive layer (35) and a second support layer (324) stacked along the first direction, and the support structure (4) is located in the stack sub-structure and extends along the first direction.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Duan, as taught by Zhao. The ordinary artisan would have been motivated to modify Duan in the above manner for purpose of avoiding the occurrence of a short circuit and improve the capacitance ([0005] of Zhao).
Regarding Claim 8
FIG. 1 of Zhao discloses a material of the first dielectric layer (31) is different from a material of the first support layer, and is different from a material of the second support layer [0056].
Regarding Claim 9
The recitation “an etching-selectivity ratio of a material of the first dielectric layer to a material of the first support layer is greater than 10:1, and an etching-selectivity ratio of the material of the first dielectric layer to a material of the second support layer is greater than 10:1”, said ratio is related to the manufacturing processes and costs. Therefore, said ratio is considered to be a result effective variable. The claim to a specific ratio therefore constitutes an optimization of ranges. In re Huang, 100 F.3d 135, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996). It would have been obvious to one of ordinary skill in the art at the time of the invention to use the parameters as claimed, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art (MPEP 2144.05).
Regarding Claim 20
FIG. 4 of Duan discloses a semiconductor device (20), comprising: a first semiconductor structure, comprising: a stack structure comprising a first dielectric layer (lower 106), a second dielectric layer (upper 106), and a stack sub-structure stacked along a first direction; and a plurality of capacitor structures (104) extending through the stack structure along the first direction, wherein a size of a portion of the capacitor structure located in the first dielectric layer along a second direction is greater than a size of a portion of the capacitor structure located in the second dielectric layer along the second direction; and the second direction is perpendicular to the first direction.
Duan is silent with respect to “a peripheral circuit coupled to the semiconductor device and configured to control at least one operation of the semiconductor device”.
FIG. 1 of Zhao discloses a similar semiconductor device, comprising a peripheral circuit (2) coupled to the semiconductor device and configured to control at least one operation of the semiconductor device.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Duan, as taught by Zhao. The ordinary artisan would have been motivated to modify Duan in the above manner for purpose of avoiding the occurrence of a short circuit and improve the capacitance ([0005] of Zhao).
Pertinent Art
U.S. Patent Pub. No. 2009/0179246, 20230371236, CN 107968044.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHENG-BAI ZHU whose telephone number is (571)270-3904. The examiner can normally be reached on 11am – 7pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on (571)270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHENG-BAI ZHU/Primary Examiner, Art Unit 2897
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