DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6/21/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claims Status
Claims 1-20 are currently pending and being examined.
Allowable Subject Matter
Claims 9-15 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
A. Re claim 9, the prior art cannot anticipate, or render obvious the limitations of: a substrate having a plurality of indentations at the first surface, wherein each of the plurality of indentations has a floor; and a second semiconductor die including: an active surface facing the first surface of the substrate of the first semiconductor die, wherein the active surface of the second semiconductor die is in direct contact with the outer surface of each of the plurality of thermal pads of the first semiconductor die, in combination with the additionally claimed features of claim 9.
In Re claims 10-15, they are allowable due to their dependence from claim 9.
Claims 3, 5-6, 8; 18 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
A. Re claim 3, the prior art cannot be used to satisfy the limitations of: wherein the TSV has a first longitudinal footprint, and wherein the thermal pad has a second longitudinal footprint smaller than the first longitudinal footprint, in combination with the additionally claimed features of claim 1.
B. Re claim 5, the prior art cannot be used to satisfy the limitations of: the semiconductor die further comprising a passivation material formed on the third surface within the indentation, wherein the TSV extends through the passivation material, and wherein the second portion of the metallization structure is spaced apart from the semiconductor substrate by the passivation material, in combination with the additionally claimed features of claim 1.
C. Re claim 6, the prior art cannot be used to satisfy the limitations of: wherein the passivation material is isolated to the third surface in the indentation, in combination with the additionally claimed features of claims 1 and 5.
D. Re claim 8, the prior art cannot be used to satisfy the limitations of: wherein the TSV has a first cross-sectional area, and wherein the thermal pad has a second cross-sectional area smaller than the first cross-sectional area, in combination with the additionally claimed features of claim 1.
E. Re claim 18, the prior art cannot be used to satisfy the limitations of: wherein at least a portion of the first surface of the semiconductor substrate outside of the indentation is exposed, in combination with the additionally claimed features of claim 16.
F. Re claim 20, the prior art cannot be used to satisfy the limitations of: wherein the upper surface of the interconnect has a first surface area, and wherein the top surface of the thermal pad has a second surface area smaller than the first surface area, in combination with the additionally claimed features of claim 16.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 2 is rejected under 35 U.S.C. 112(b), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
A. Claim 2 recites the limitation “the TSV further includes” and "the sidewall of the end portion" in line 1 and line 4, respectively. There is insufficient antecedent basis for the limitation "the sidewall of the end portion" in the claim.
For examination purposes and consistency with claim 1, “the TSV further includes” in line 1 will be interpreted to read as “the TSV end portion further includes”. A clarifying amendment as suggested or similar would overcome the rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2, 4 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Gan (US 2004/0259325 A1-IDS prior art) in view of Cobbley et al (US 2011/0180936 A1, hereafter Cobbley) and Kwon et al (US 2011/0133333 A1-IDS prior art, hereafter Kwon).
Re claim 1, Gan discloses in FIG. 3 (with references to FIG. 1) a semiconductor die, comprising:
a semiconductor substrate (silicon 50; [0021]) including a first surface (lowermost horizontal plane at 52), a second surface (uppermost horizontal plane at 56) opposite to (above) the first surface, and an indentation (54; [0021]) on the first surface having third surface (intermediate horizontal plane of 50) positioned between the first surface and the second surface;
a through-substrate via (TSV; filled via 55; [0021] and [0023]) extending at least partially through the semiconductor substrate (50), wherein the TSV (55) includes an end portion (exposed part; [0023]) projecting from the third surface of the indentation, and wherein the end portion has an upper surface (lower plane) that is coplanar (level) with the first surface of the semiconductor substrate (50);
a metallization structure (52; [0021]) connected to the TSV (55), wherein the metallization structure includes a first portion (lower horizontal plane) on the upper surface; and
a thermal pad (52 contacting 50; [0021]) having a lower surface (uppermost horizontal plane) in direct contact with (physically touching) the first surface of the semiconductor substrate (50) and a top surface (lowermost horizontal plane) opposite (below) the lower surface, and wherein the thermal pad (52 contacting 50) is an isolated structure (electrically inactive) on the first surface.
Gan fails to disclose the second surface (uppermost horizontal plane at 56) opposite to (above) the first surface (lowermost horizontal plane at 52) having one or more electrical circuits; the through-substrate via (55) connected to the one or more electrical circuits; and wherein the metallization structure includes a second portion extending toward the third surface in the indentation.
However,
A. Cobbley discloses in FIG. 7 (with references to FIGS. 1 and 8) a semiconductor die (100’’; [0043]), comprising: a second surface (12; [0013]) opposite to (below) a first surface (13; [0034]) having one or more electrical circuits (of 12; [0013]); and a through-substrate via (110; [0043]) connected to ([0038]) the one or more electrical circuits (of 12).
And,
B. Kwon discloses in FIG. 16D (with references to FIGS. 13-14D) a semiconductor die, comprising: wherein a metallization structure (60; [0110] and [0129]) includes a second portion (60b; [0119]) extending toward a third surface (12; [0119]) in an indentation (17; [0133]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Gan by adding the one or more electrical circuits of Cobbley, such that the second surface (uppermost horizontal plane at 56) opposite to (above) the first surface (lowermost horizontal plane at 52) having one or more electrical circuits; the through-substrate via (55) connected to the one or more electrical circuits, creating a range of electronic devices (e.g. computer, controller, phone, camera, etc.; Cobbley; [0043]), and using the metallization structure configuration of Kwon, wherein the metallization structure includes a second portion extending toward the third surface in the indentation, increasing the adhesion strength between the metallization structure and the TSV.
Re claim 2, Gan discloses the semiconductor die of claim 1.
But, fails to disclose wherein the TSV (55) end portion (exposed part) further includes a sidewall surrounded by an isolation lining isolating the TSV from the semiconductor substrate, and wherein the second portion of the metallization structure extends at least partially around the isolation lining such that the second portion is laterally spaced apart from the sidewall of the end portion by the isolation lining.
However, Kwon discloses wherein a TSV end portion (part of 20 above surfaces 12/17; [0099]; [0101] and [0131]) further includes a sidewall (left/right vertical planes) surrounded by an isolation lining (22; [0119]) isolating the TSV (20) from a semiconductor substrate (10; [0097] and [0101]), and wherein the second portion (60b) of the metallization structure (60) extends at least partially around the isolation lining (22) such that the second portion (60b) is laterally (in cross-section) spaced apart (separated) from the sidewall (left/right vertical planes) of the end portion by the isolation lining, as would be part of the increased adhesion strength between the metallization structure and the TSV discussed for claim 1.
Re claim 4, Gan discloses the semiconductor die of claim 1, wherein the top surface of the thermal pad (52 contacting 50) is coplanar with (level) an uppermost surface (lowermost plane) of the metallization structure (52).
Re claim 7, Gan discloses the semiconductor die of claim 1, wherein the thermal pad (52 contacting 50) has a first thickness (vertical extension) and the first portion (lower horizontal plane) of the metallization structure (52) has a second thickness (vertical extension), wherein the first thickness is generally equal to (co-planar with) the second thickness.
Claims 16-17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Gan in view of Kwon.
Re claim 16, Gan discloses in FIG. 3 (with references to FIG. 1) a semiconductor die, comprising:
a semiconductor substrate including a first surface and an indentation on the first surface having a second surface at a floor of the indentation (see claim 1);
an interconnect extending at least partially through the semiconductor substrate, wherein the interconnect includes an end portion projecting from the second surface, and wherein the end portion has an upper surface facing away from the second surface (see claim 1);
a metallization structure connected to the interconnect, wherein the metallization structure includes a first portion on the upper surface (see claim 1); and
a thermal pad having a lower surface in direct contact with the first surface of the semiconductor substrate and a top surface opposite the lower surface, wherein the thermal pad is electrically isolated on the first surface of the semiconductor substrate (see claim 1).
Gan fails to disclose wherein the metallization structure includes a second portion extending at least partially around a sidewall of the end portion.
However,
Kwon discloses in FIG. 16D (with references to FIGS. 13-14D) a semiconductor die, comprising: wherein a metallization structure (60; [0110] and [0129]) includes a second portion (60b; [0119]) extending at least partially around a sidewall (left/right vertical planes) of an end portion (part of 20 above surfaces 12/17; [0131]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Gan by using the metallization structure configuration of Kwon, wherein the metallization structure includes a second portion extending at least partially around a sidewall of the end portion, increasing the adhesion strength between the metallization structure and the TSV.
Re claim 17, Gan discloses the semiconductor die of claim 16.
But, fails to disclose the semiconductor die further comprising a passivation material formed over the second surface at the floor of the indentation, wherein the second portion of the metallization structure is spaced apart from the second surface by the passivation material.
However, Kwon discloses a passivation material (34; [0118]) formed over a second surface (upper plane of 17; [0132]) at a floor (base of 17; [0132]) of an indentation (17; [0132]), wherein the second portion (60b) of the metallization structure (60) is spaced apart (separated) from the second surface (upper plane of 17) by the passivation material (34), as part of the structure for increasing the adhesion strength between the metallization structure and the TSV discussed for claim 16.
Re claim 19, Gan discloses the semiconductor die of claim 16, wherein the first surface (lowermost horizontal plane at 52) of the semiconductor substrate (50) is coplanar with the upper surface (lower plane) of the interconnect (55).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 20120086122 A1 discloses metallization structures comprising second portions and passivation materials separating sidewalls of TSVs from the second portions without being applicable to any of claims 1; 9; and 16, alone or in combination, for systems for improved heat dissipation of the stacked semiconductor dies by including metallic thermal pads between the dies in the stack.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC W JONES whose telephone number is (408) 918-9765. The examiner can normally be reached M-F 7:00 AM - 6:00 PM PT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIC W JONES/Primary Examiner, Art Unit 2892
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