Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/16/2026 has been entered.
Response to Amendment
Applicant's amendment dated 04/02/2026 in which claims 1, 2, 9, 10, 16, 17 were amended has been entered of record. Currently, claims 1-20 are pending in light of the amendment.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless -
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 9 and 16 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by WO 2022/015967 A1 (herein Gupta).
Claim 1. A method, comprising: applying, to a plurality of memory cells programmed to represent a plurality of weights (array of HEM cells, Gupta Fig 5, storing bits and a resistance state based on the stored value, thus storing weights), a plurality of voltages according to a bit slice having a slice weight in an input (bit slice operation in which different arrays process different bits such as MSB to LSB, each having different significance corresponding to a slice weight, Gupta); generating, in a line connected to the plurality of memory cells, a current resulting from the plurality of memory cells responsive to the plurality of voltages (input voltages to the cells to generating output currents based on the resistance states wherein the currents are accumulating along the column, Gupta [0007]); and applying, to an analog to digital converter coupled to the line (Gupta teaches converting the accumulated current to a voltage and digitizing the current using an analog to digital converter, Gupta [0007]), a resolution control according to the slice weight (quantization and reduced precision outputs, Gupta [0067]).
Claim 9. A device, comprising: a plurality of memory cells programmable to represent a plurality of weights (array of HEM cells, Gupta Fig 5, storing bits and a resistance state based on the stored value, thus storing weights); a plurality of wordlines connected to the plurality of memory cells (WLs as seen in Fig 5); a bitline connected to collect currents going through the plurality of memory cells (BL1, as seen in Fig 5, which accumulates output current from the memory cells); voltage drivers operable to apply, to the plurality of memory cells via the plurality of wordlines, a plurality of voltages according to a bit slice having a slice weight in an input (applying input voltages to the array and bit slice operation across multiple arrays corresponding to different bit significance); an analog to digital converter coupled to the bitline and configured with a resolution control (ADC coupled to the output to convert the signal, Fig 6); and a logic circuit configured to apply the resolution control according to the slice weight in measurement of, using the analog to digital converter, at least one first bit of a quantity representative of a magnitude of a current in the bitline responsive to the plurality of voltages being applied to the plurality of memory cells (quantization and reduced precision outputs, Gupta [0067]).
Claim 16. A system, comprising: a memory cell array (array of HEM cells, Gupta Fig 5) having a plurality of memory cells connected to a plurality of wordlines and a bitline (WLs and BL1 as seen in Fig 5); voltage drivers; and at least one analog to digital converter (ADC coupled to the output to convert the signal, Fig 6); a processor configured to: program the plurality of memory cells to store a plurality of weights (programming memory cells to store data bits that determine resistance state corresponding to weights); identify a bit slice having a slice weight in an input (bit slice operation across multiple arrays corresponding to different bit significance); instruct the voltage drivers to apply, via the wordlines, a plurality of voltages according to the bit slice (applying input voltages to the array and performing bit sliced processing across multiple arrays with different bits); and instruct the analog to digital converter to generate a truncated output from measurement of a current in the bitline resulting from the plurality of memory cells responsive to the plurality of voltages (current in bitlines from applied voltages and stored weights converting the signal via the analog to digital converter).
Allowable Subject Matter
Claims 2-8, 20-25, 17-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 2. Measuring, using the analog to digital converter, at least one first bit of a quantity representative of a magnitude of the current in the line responsive to the plurality of voltages; summing a plurality of truncated outputs resulting from a plurality of bit slices having a plurality of slice weights respectively in the input, the plurality of truncated outputs including a truncated output having the at least one first bit, in combination with other limitations.
Claim 10. To sum a plurality of truncated outputs resulting from a plurality of bit slices having a plurality of slice weights respectively in the input, the plurality of truncated outputs including a truncated output having the at least one first bit but, in combination with other limitations.
Claim 17. Wherein the processor configured to instruct the analog to digital converter to generate the truncated output from measurement of the current in the bitline resulting from the plurality of memory cells responsive to the plurality of voltages, wherein the analog to digital converter to measure at least one first bit of a quantity representative of a magnitude of the current in the line responsive to the plurality of voltages; wherein the system is configured sum a plurality of truncated outputs, resulting from a plurality of bit slices having a plurality of slice weights respectively in the input, to provide an approximated result of a sum of the input having a plurality of elements weighted by the plurality of weights respectively; and the system, in combination with other limitations.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jason Lappas whose telephone number is (571 )270-1272. The examiner can normally be reached on M-F 7:30AM-5:00PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Amir Zarabian can be reached on (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Jason Lappas/
Primary Examiner, Art Unit 2827
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