Prosecution Insights
Last updated: August 18, 2026
Application No. 18/751,130

SEMICONDUCTOR DEVICE WITH EMBEDDED COOLING

Non-Final OA §102§103§112
Filed
Jun 21, 2024
Examiner
ZHU, SHENG-BAI
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
International Business Machines Corporation
OA Round
1 (Non-Final)
62%
Grant Probability
Moderate
1-2
OA Rounds
7m
Est. Remaining
68%
With Interview

Examiner Intelligence

Grants 62% of resolved cases
62%
Career Allowance Rate
446 granted / 716 resolved
-5.7% vs TC avg
Moderate +6% lift
Without
With
+6.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
61 currently pending
Career history
782
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
69.2%
+29.2% vs TC avg
§102
22.7%
-17.3% vs TC avg
§112
7.0%
-33.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 716 resolved cases

Office Action

§102 §103 §112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Detailed Action Claim Rejections – 35 U.S.C. 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 12 recites the limitation "an active layer" twice. It is unclear whether the second recited "an active layer" was intended to relate back to the first recited "an active layer" or to set forth an additional active layer. For the purpose of examination, the Examiner interprets the second recited "an active layer" as the active layer. Claims 13-20 depend from Claim 12. Claim Rejections – 35 U.S.C. 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AlA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Claims 1 and 5-7 rejected under 35 U.S.C. 102(a)(1) as being anticipated by King (U.S. Patent Pub. No. 2012/0228779). Regarding Claim 1 FIG. 10 of King discloses an electrical device, comprising: a plurality of layers coupled with column interconnect structures (1015), the plurality of layers comprising: at least one active layer (1010) having a back end of line (BEOL) layer (1011); and at least one heat transfer die layer (1014) having no BEOL layer or a BEOL layer having a through thermal resistance of less than 2 Cmm.sup.2/W, wherein the at least one heat transfer die layer is in contact with a coolant [0052]. Furthermore, said resistance is related to the thermal release performance. Therefore, said resistance is considered to be a result effective variable. The claim to a specific resistance therefore constitutes an optimization of ranges. In re Huang, 100 F.3d 135, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996). It would have been obvious to one of ordinary skill in the art at the time of the invention to use the parameters as claimed, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art (MPEP 2144.05). Regarding Claim 5 FIG. 10 of King discloses each of the plurality of layers comprise a substrate including a material that is at least one of silicon, silicon germanium, silicon doped with carbon (Si:C), germanium (Ge), silicon germanium doped with carbon (SiGe:C), silicon carbide, type III-V compound semiconductor materials, or a combination thereof [0041]. Regarding Claim 6 The limitation “a total through thermal resistance of the at least one active layer is more than 2 Cmm.sup.2/W” is related to material property. King discloses an active layer with substantially identical composi-tion. Where the claimed and prior art products are identi-cal or substantially identical in structure or composi-tion, or are produced by identical or substantially identical processes, a prima facie case of either antici-pation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). MPEP2112.01 Regarding Claim 7 FIG. 10 of King discloses each of the at least one active layer is in contact with the coolant from one side. Claim 1 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Suo (CN 116364678). Regarding Claim 1 FIG. 1 of Suo discloses an electrical device, comprising: a plurality of layers coupled with column interconnect structures (31), the plurality of layers comprising: at least one active layer (3) having a back end of line (BEOL) layer (12); and at least one heat transfer die layer (32) having no BEOL layer or a BEOL layer having a through thermal resistance of less than 2 Cmm.sup.2/W, wherein the at least one heat transfer die layer is in contact with a coolant (liquid silicon). Claims 1-19 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chainer (U.S. Patent Pub. No. 2017/0186728). Regarding Claim 1 FIG. 1 of Chainer discloses an electrical device, comprising: a plurality of layers coupled with column interconnect structures (116), the plurality of layers comprising: at least one active layer (104) having a back end of line (BEOL) layer (112); and at least one heat transfer die layer (106) having no BEOL layer or a BEOL layer having a through thermal resistance of less than 2 Cmm.sup.2/W [0026], wherein the at least one heat transfer die layer is in contact with a coolant [0053]. Furthermore, said resistance is related to the thermal release performance. Therefore, said resistance is considered to be a result effective variable. The claim to a specific resistance therefore constitutes an optimization of ranges. In re Huang, 100 F.3d 135, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996). It would have been obvious to one of ordinary skill in the art at the time of the invention to use the parameters as claimed, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art (MPEP 2144.05). Regarding Claim 2 FIG. 10 of Chainer discloses a cooling channel between each of two adjacent layers. Regarding Claim 3 Chainer discloses the coolant is a dielectric coolant [0066]. Regarding Claim 4 FIG. 1 of Chainer discloses at least one of the column interconnect structures (116) comprises at least one through silicon via (TSV); and at least one TSV comprises at least one metal layer [0033]. Regarding Claim 5 FIG. 1 of Chainer discloses each of the plurality of layers comprise a substrate (102) including a material that is at least one of silicon, silicon germanium, silicon doped with carbon (Si:C), germanium (Ge), silicon germanium doped with carbon (SiGe:C), silicon carbide, type III-V compound semiconductor materials, or a combination thereof [0025]. Regarding Claim 6 The limitation “a total through thermal resistance of the at least one active layer is more than 2 Cmm.sup.2/W” is related to material property. Chainer discloses an active layer with substantially identical composi-tion (silicon). Where the claimed and prior art products are identi-cal or substantially identical in structure or composi-tion, or are produced by identical or substantially identical processes, a prima facie case of either antici-pation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). MPEP2112.01 Regarding Claim 7 FIG. 1 of Chainer discloses each of the at least one active layer is in contact with the coolant from one side. Regarding Claim 8 Chainer discloses a total through thermal resistance of the at least one heat transfer die layer is less than 2 Cmm.sup.2/W [0026]. Furthermore, said resistance is related to the thermal release performance. Therefore, said resistance is considered to be a result effective variable. The claim to a specific resistance therefore constitutes an optimization of ranges. In re Huang, 100 F.3d 135, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996). It would have been obvious to one of ordinary skill in the art at the time of the invention to use the parameters as claimed, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art (MPEP 2144.05). Regarding Claim 9 FIG. 10 of Chainer discloses each of the at least one active layer is coupled with at least one heat transfer die layer (106) on both sides of the at least one layer via the column interconnect structures (116). Regarding Claim 10 The limitation “the at least one active layer is etched on one side to increase a surface area of the at least one active layer; and the at least one heat transfer die layer is etched on both sides” is considered to be a process or functional limitation. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985), MPEP 2113. With respect to “configured to increase the surface area of the at least one heat transfer die layer”, said configuration is related to the thermal release performance. Therefore, said configuration is considered to be a result effective variable. The claim to a specific configuration therefore constitutes an optimization of ranges. In re Huang, 100 F.3d 135, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996). It would have been obvious to one of ordinary skill in the art at the time of the invention to use the parameters as claimed, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art (MPEP 2144.05). Regarding Claim 11 FIG. 10 of Chainer discloses the column interconnect structures comprise a metal without a substrate. Regarding Claim 12 FIG. 10 of Chainer discloses a method for constructing an electrical device, the method comprising: creating a first array of a plurality of column interconnect structures (116), wherein each of the plurality of column interconnect structures includes at least one through silicon via (TSV); coupling an active layer (110) to one end of the first array of plurality of column interconnect structures; coupling a first heat transfer die layer (106) to another end of the first array of plurality of column interconnect structures; creating a second array of plurality of column interconnect structures; coupling one end the second array of plurality of column interconnect structures to an active layer; and coupling a second heat transfer die layer to another end of the second array of plurality of column interconnect structures. Regarding Claim 13 FIG. 10 of Chainer discloses creating a plurality of cooling channels between two adjacent layers and the plurality of interconnect structures; and flowing a coolant in the plurality of cooling channels Regarding Claim 14 FIG. 1 of Chainer discloses the active layer, the first heat transfer die, and the second heat transfer die each comprise a substrate including one or more materials selected from silicon, silicon germanium, silicon doped with carbon (Si:C), germanium (Ge), silicon germanium doped with carbon (SiGe:C), silicon carbide, type III-V compound semiconductor [0025]. Regarding Claim 15 The limitation “a total through thermal resistance of the at least one active layer is more than 2 Cmm.sup.2/W” is related to material property. Chainer discloses an active layer with substantially identical composi-tion (silicon). Where the claimed and prior art products are identi-cal or substantially identical in structure or composi-tion, or are produced by identical or substantially identical processes, a prima facie case of either antici-pation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). MPEP2112.01 Regarding Claim 16 FIG. 1 of Chainer discloses maintaining a total through thermal resistance of the each of the first heat transfer die layer and the second heat transfer die layer less than 2 Cmm.sup.2/W [0026]. Regarding Claim 17 FIG. 10 of Chainer discloses creating a third array (FIG. 9) of a plurality of column interconnect structures; and coupling one end of the third array of the plurality of column interconnect structures to the second heat transfer die layer. Regarding Claim 18 FIG. 11 of Chainer discloses coupling a third heat transfer die layer to another end of the third array of plurality of column interconnect structures. Regarding Claim 19 FIG. 11 of Chainer discloses coupling the active layer (110) with at least one heat transfer die layer from both sides via the column interconnect structures (116). Claim Rejections – 35 U.S.C. 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 2-4 rejected under 35 U.S.C. 103 as being unpatentable over Suo, in view of Matsuzawa (U.S. Patent Pub. No. 2020/0075452). Regarding Claim 2 Suo discloses Claim 1. Suo is silent with respect to “a cooling channel between each of two adjacent layers”. FIG. 10 of Matsuzawa discloses a similar electrical device, comprising a cooling channel (4) between each of two adjacent layers. It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Suo, as taught by Matsuzawa. The ordinary artisan would have been motivated to modify Suo in the above manner for purpose of effectively releasing heat from the semiconductor element ([0005] of Matsuzawa). Regarding Claim 3 Suo discloses the coolant is a dielectric coolant (liquid silicon). Regarding Claim 4 FIG. 1 of Suo discloses at least one of the column interconnect structures (31) comprises at least one through silicon via (TSV); and at least one TSV comprises at least one metal layer. Claim 20 rejected under 35 U.S.C. 103 as being unpatentable over Chainer, in view of Leobandung (U.S. Patent Pub. No. 2019/0385928). Regarding Claim 20 Chainer discloses Claim 12. Chainer is silent with respect to “etching the active layer on one side to increase a surface area of the active layer”. FIG. 8 of Leobandung discloses a similar method, comprising etching the active layer on one side to increase a surface area of the active layer [0032, 0068]. It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the method of Chainer, as taught by Leobandung. The ordinary artisan would have been motivated to modify Chainer in the above manner for purpose of more efficient heat transfer to the coolant ([0068] of Leobandung). Pertinent Art Canaperi (U.S. Patent Pub. No. 2020/0161216), 20200161216, 20120306088, JP 5983565. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHENG-BAI ZHU whose telephone number is (571)270-3904. The examiner can normally be reached on 11am – 7pm EST. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on (571)270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SHENG-BAI ZHU/Primary Examiner, Art Unit 2897
Read full office action

Prosecution Timeline

Jun 21, 2024
Application Filed
Jul 29, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

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Prosecution Projections

1-2
Expected OA Rounds
62%
Grant Probability
68%
With Interview (+6.1%)
2y 9m (~7m remaining)
Median Time to Grant
Low
PTA Risk
Based on 716 resolved cases by this examiner. Grant probability derived from career allowance rate.

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