Prosecution Insights
Last updated: October 02, 2026
Application No. 18/751,360

SEMICONDUCTOR MEMORY DEVICE

Non-Final OA §112
Filed
Jun 24, 2024
Priority
Nov 19, 2021 — RE 10-2021-0160546 +1 more
Examiner
RAHMAN, MOHAMMAD A
Art Unit
Tech Center
Assignee
SK hynix Inc.
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
4m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
498 granted / 572 resolved
+27.1% vs TC avg
Moderate +11% lift
Without
With
+10.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
26 currently pending
Career history
583
Total Applications
across all art units

Statute-Specific Performance

§101
2.7%
-37.3% vs TC avg
§103
46.7%
+6.7% vs TC avg
§102
30.4%
-9.6% vs TC avg
§112
18.7%
-21.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 572 resolved cases

Office Action

§112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Claims 1-9 are pending and have been examined. Priority Acknowledgment is made of applicant's claim for foreign benefit based on KR10-2021-0160546 filed on 11/19/2021. The instant application is a continuation of US patent application 17839593. Claim Rejections - 35 USC § 112 The following is a quotation of the second paragraph of 35 U.S.C. 112: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-9 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Claim 1 recites: “a plurality of gate dielectric layers surrounding the active layers, respectively”. There is insufficient antecedent basis for this limitation in the claim. The applicant may recite the following to overcome this rejection: “a plurality of gate dielectric layers surrounding the plurality of active layers, respectively”. Claim 1 also recites: “a word line stack including a plurality of gate all-around conductive lines that are surround the gate dielectric layers”. There is insufficient antecedent basis for this limitation in the claim. The applicant may recite the following to overcome this rejection: “a word line stack including a plurality of gate all-around conductive lines that are surround the plurality of gate dielectric layers”. Claim 1 further recites: “word line contact plugs coupled to the conductive pads, respectively”. There is insufficient antecedent basis for this limitation in the claim. “the conductive pads” also recited in claims 2, 4, 5. Therefore, corrections required in all four claims. Claim 3 recites: “The semiconductor memory device of claim 1, wherein the edge portions of the gate all-around conductive lines are self-aligned”. There is insufficient antecedent basis for this limitation in the claim. The applicant may recite the following to overcome this rejection: “The semiconductor memory device of claim 1, wherein the edge portions of the plurality of gate all-around conductive lines are self-aligned”. Claim 4 recites: “a second edge portion coupled to the contact plugs”. There is insufficient antecedent basis for this limitation in the claim. The applicant may recite the following to overcome this rejection: “a second edge portion coupled to the word line contact plugs”. Claim 7 recites: “wherein the active layers include a semiconductor material or an oxide semiconductor material”. There is insufficient antecedent basis for this limitation in the claim. The applicant may recite the following to overcome this rejection: “wherein the plurality of active layers include a semiconductor material or an oxide semiconductor material”. Claims 2-9 depend from claim 1. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD A. RAHMAN whose telephone number is (571) 270-0168 and email is mohammad.rahman5@uspto.gov. The examiner can normally be reached on Mon-Fri 8:00-5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado can be reached on (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see https://ppair-my.uspto.gov/pair/PrivatePair. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MOHAMMAD A RAHMAN/ Primary Examiner, Art Unit 2898
Read full office action

Prosecution Timeline

Jun 24, 2024
Application Filed
Aug 17, 2026
Non-Final Rejection mailed — §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12745509
LIGHT-EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME, DISPLAY SUBSTRATE
3y 1m to grant Granted Sep 22, 2026
Patent 12738315
NEUROMORPHIC SYNAPSE DEVICE WITH EXCELLENT LINEARITY CHARACTERISTICS AND OPERATING METHOD THEREOF
4y 7m to grant Granted Sep 15, 2026
Patent 12740053
SEMICONDUCTOR DEVICE INCLUDING DIFFERENT CONDUCTIVE LINES
3y 0m to grant Granted Sep 15, 2026
Patent 12740139
THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
2y 7m to grant Granted Sep 15, 2026
Patent 12740150
INTEGRATION OF STACKED LOGIC DEVICE WITH PASSIVE DEVICE
3y 1m to grant Granted Sep 15, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
98%
With Interview (+10.8%)
2y 8m (~4m remaining)
Median Time to Grant
Low
PTA Risk
Based on 572 resolved cases by this examiner. Grant probability derived from career allowance rate.

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