Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5, 6, 7, 8, 14, 15, 16, 19, 21, 22. 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jo (US 20230069681) in view of Xu (CN 111210784).
Regarding claim 5 Jo teaches a display device (fig.3) comprising:
a pixel (fig.3, PX) including a light emitting element connected ([0015] In an embodiment, each of the plurality of pixels may include a light emitting element and a pixel driving circuit connected to the light emitting element) to a driving voltage line (fig.3, DL1) transferring a driving voltage (fig. 3, [0016]);
a sensor including a light sensing element ([0088] Each of the sensors FX includes a light sensing element OPD) connected to the driving voltage line and a reset voltage line receiving a reset voltage ([0077] fig. 3);
a driving controller (fig. 3, 100) configured to receive an image signal (Fig.3, RGB) and a control signal (fig.3, CTRL); and
a voltage generator (fig.3, 600) configured to generate the driving voltage and the reset voltage (fig.3, ELVDD, ELVSS, VRST), wherein the driving controller is configured to:
determine a voltage level of the driving voltage based on the image signal and the control signal ([0125]);
determine a voltage level of the reset voltage based on the determined voltage level of the driving voltage ([0139]); and
output the voltage control signal (fig.6, GWa) corresponding to the voltage level of the driving voltage ([0125]) and the voltage level of the reset voltage ([0139]).
Jo is silent on determine a voltage level of the reset voltage based on the determined voltage level of the driving voltage, and change the voltage level of the reset voltage in response to the determined voltage level of the driving voltage;
However, Xu teaches determine a voltage level of the reset voltage based on the determined voltage level of the driving voltage, and change the voltage level of the reset voltage in response to the determined voltage level of the driving voltage (On the other hand, when providing one or more reset voltage Vrst changes according to one or more drive voltage VDD, because providing one or more reset voltage Vrst matched with one or more drive voltage VDD provided to the display panel 110, … That is, it can change the reset voltage Vrst to match the changed driving voltage VDD);
Therefore, it would have been obvious to one of the ordinary skilled in the art to combine Jo in light of Xu teaching so that it may include determine a voltage level of the reset voltage based on the determined voltage level of the driving voltage, and change the voltage level of the reset voltage in response to the determined voltage level of the driving voltage;
The motivation is to provide data driving circuit, a display panel that can prevent the flicker to improve display quality.
Regarding claim 6, Jo teaches wherein the sensor comprises (fig. 6): the light sensing element (OPD) connected between a sensing node (sensing node SN1) and the driving voltage line (ELVSS);
a first transistor (ST1) connected between the reset voltage line (VRST) and the sensing node (SN1);
a second transistor (ST2) connected between a sensor driving voltage line (VL1) and an intermediate node (SN2) and including a gate electrode connected to sensing node; and
a third transistor (ST3) connected between the intermediate node (SN2) and a readout line (RLi) and including a gate electrode connected to a scan line (Gwa).
Regarding claim 7, Jo teaches wherein the first transistor (fig. 6, ST1 n type) is a transistor of a first type (n type), and wherein the second transistor (ST2) and the third transistor (ST3) are transistors of a second type (p type) different from the first type (n type).
Regarding claim 8, Jo teaches wherein the light sensing element (fig. 6, OPD) includes a cathode connected to the driving voltage line (ELVSS) and an anode connected to the sensing node (SN1), and wherein the light emitting element (ED) includes a cathode connected to the driving voltage line (ELVSS) and an anode.
Regarding claim 14 Jo teaches a display device (fig.3) comprising:
a display panel including pixels (fig.3, PX) and sensors (fig.3, FX);
a driving controller (fig. 3, 100) configured to receive an image signal (Fig.3, RGB) and a control signal (fig.3, CTRL); and
a voltage generator (fig.3, 600) configured to generate a driving voltage and a reset voltage (fig.3, ELVDD, ELVSS, VRST),
wherein each of the sensors includes a light sensing element connected to a driving voltage line receiving the driving voltage and a reset voltage line receiving the reset voltage, and
wherein the driving controller is configured to:
determine a voltage level of the driving voltage based on the image signal and the control signal ([0125]);
determine a voltage level of the reset voltage based on the determined voltage level of the driving voltage ([0139]); and
output the voltage control signal (fig.6, GWa) corresponding to the voltage level of the driving voltage ([0125]) and the voltage level of the reset voltage ([0139]).
Jo is silent on determine a voltage level of the reset voltage based on the determined voltage level of the driving voltage and information regarding a voltage distribution of the driving voltage provided to the display panel (On the other hand, when providing one or more reset voltage Vrst changes according to one or more drive voltage VDD, because providing one or more reset voltage Vrst matched with one or more drive voltage VDD provided to the display panel 110, … That is, it can change the reset voltage Vrst to match the changed driving voltage VDD also see fig. 12).
Therefore, it would have been obvious to one of the ordinary skilled in the art to combine Jo in light of Xu teaching so that it may include determine a voltage level of the reset voltage based on the determined voltage level of the driving voltage and information regarding a voltage distribution of the driving voltage provided to the display panel.
The motivation is to provide data driving circuit, a display panel that can prevent the flicker to improve display quality.
Regarding claim 15, Jo teaches a sensor driver (fig. 3, 300) configured to output scan signals (GW1) for driving the pixels (PX) and to output reset signals (fig. 6, RST) for driving the sensors ([0091]).
Regarding claim 16, Jo teaches wherein the voltage generator further generates a reset control voltage in response to the voltage control signal, and wherein the sensor driver outputs the reset signals corresponding to a voltage level of the reset control voltage (fig. 3, fig. 6).
Regarding claim 19 Jo teaches wherein the first sensor comprises: a first light sensing element (fig.6, ED) connected between a first sensing node (SN1) and the driving voltage line (ELVSS); and
a first transistor (ST1) connected between the reset voltage line (VRST) and the first sensing node (SN1) and including a gate electrode receiving the first reset signal (RST), and wherein the second sensor comprises: a second light sensing element connected between a second sensing node and the driving voltage line; and a second transistor (ST2) connected between the reset voltage line (RSTL) and the second sensing node (SN2) and including a gate electrode receiving the second reset signal (fig. 6, since sensing element OPD, sensing node SN1 will be repeated for second time).
Regarding claim 21 Jo in view of Xu teach wherein the voltage level of the reset
voltage is based on the determined voltage level of the driving voltage and information regarding a voltage distribution of the driving voltage provided to a display panel (Xu: On the other hand, when providing one or more reset voltage Vrst changes according to one or more drive voltage VDD, because providing one or more reset voltage Vrst matched with one or more drive voltage VDD provided to the display panel 110, … That is, it can change the reset voltage Vrst to match the changed driving voltage VDD also see fig. 12).
Regarding claim 22, the limitations are significantly similar to the limitations of claim 5 so rejected same way.
Regarding claim 23, the limitations are significantly similar to the limitations of claim 21 so rejected same way.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jo (US 20230069681) in view of Xu (CN 111210784) and further in view of Kwak (US 20210325943).
Regarding claim 17, Jo is silent on wherein the display panel includes a first area and a second area, and wherein the sensors include a first sensor disposed in the first area and a second sensor disposed in the second area.
However, Kwak teaches silent wherein the display panel includes a first area and a second area, and wherein the sensors include a first sensor disposed in the first area and a second sensor disposed in the second area ([0011]).
Therefore, it would have been obvious to one of the ordinary skilled in the art to combine Jo in light of Kwak teaching so that it may include wherein the display panel includes a first area and a second area, and wherein the sensors include a first sensor disposed in the first area and a second sensor disposed in the second area.
The motivation is to extend the active area of the display.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jo (US 20230069681) in view of Xu and further in view of Kwak (US 20210325943) and Park (US 20050253796).
Regarding claim 18 Jo in view of Kwak teaches first reset signal and first sensor and second sensor (Kwak: [0011]).
But is silent on a second reset signal, and wherein a voltage level of the first reset signal and a voltage level of the second reset signal are different from each other.
However, Park teaches a second reset signal, and wherein a voltage level of the first reset signal and a voltage level of the second reset signal are different from each other (Claim 12: driving method of a liquid crystal display of claim 9, wherein a voltage level of the first reset waveform is different from a voltage level of the second reset waveform).
Therefore, it would have been obvious to one of the ordinary skilled in the art to combine Jo in light of Park teaching so that it may include second reset signal, and wherein a voltage level of the first reset signal and a voltage level of the second reset signal are different from each other.
The motivation is to improve light transmission rate of the color filters of the display.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jo (US 20230069681) in view of Xu and further Cha (US 20220336561).
Regarding claim 20 Lo is silent on wherein the display panel further comprises: a base layer; a circuit layer disposed on the base layer, wherein the first transistor and the second transistor are disposed in the circuit layer; and an element layer disposed on the circuit layer and including the first light sensing element and the second light sensing element.
However, Cha teaches wherein the display panel further comprises: a base layer; a circuit layer disposed on the base layer, wherein the first transistor and the second transistor are disposed in the circuit layer; and an element layer disposed on the circuit layer and including the first light sensing element and the second light sensing element (see fig. 13A-13B below and [0214] [0215] ).
PNG
media_image1.png
413
627
media_image1.png
Greyscale
PNG
media_image2.png
592
787
media_image2.png
Greyscale
Therefore, it would have been obvious to one of the ordinary skilled in the art to combine Jo in light of Cha teaching so that it may include: a base layer; a circuit layer disposed on the base layer, wherein the first transistor and the second transistor are disposed in the circuit layer; and an element layer disposed on the circuit layer and including the first light sensing element and the second light sensing element.
The motivation is to provide a display device including a display panel, in which a sensor for biometric information recognition.
Allowable Subject Matter
Claims 9-13 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claim(s) 5 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
-KR 20230260459 is related prior art as it discloses some aspects of the independent claims.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TOWFIQ ELAHI whose telephone number is (571)270-1687. The examiner can normally be reached M-F: 10AM-3PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Boddie can be reached at (571)272-0666. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TOWFIQ ELAHI/Primary Examiner, Art Unit 2625
Prosecution Insights