DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Oh et al. (US 2022/0059442) [Hereinafter Oh], Jeng et al. (US 2019/0131284) [Hereinafter Jeng], & Kim et al (US 2020/0402952).
Regarding claim 1, Oh teaches A semiconductor package comprising:
a lower package substrate [fig. 9, substrate 500, para 75] including a lower redistribution insulation layer [fig. 9, dielectric layer 101L/201/301/103, para 76] and
a lower redistribution pattern [fig. 9, redistribution patterns 110L/210/310, para 78-80] positioned within the lower redistribution insulation layer (fig. 9, 101L/201/301/103) ;
a semiconductor chip [fig. 9, semiconductor apparatus 700, para 85] mounted on the lower package substrate (fig. 9, 500);
a connection terminal [fig. 9, connection member 708, para 85] positioned between the lower package substrate (fig. 9, 500) and the semiconductor chip (fig. 9, 700), and connecting the semiconductor chip (fig. 9, 700) to the lower package substrate (fig. 9, 500);
a molding member [fig. 9, molding member 750, para 86] positioned on the lower package substrate (fig. 9, 500) and covering at least a portion of the semiconductor chip (fig. 9, 700); and
a conductive post [fig. 9, mold via 730, para 86] positioned within the molding member (fig. 9, 750) and connected to the lower redistribution pattern [fig. 9, 110L/210/310],
Oh fails to explicitly disclose wherein the molding member and the conductive post define a trench,
wherein the trench includes a first inner surface recessed toward the lower package substrate from an upper surface of the molding member and
a second inner surface corresponding to a side surface of the conductive post,
wherein the side surface of the conductive post extends beyond the first inner surface of the trench in a direction away from the lower package substrate, and
wherein the first inner surface of the molding member includes a first curved surface connecting the upper surface of the molding member to the side surface of the conductive post.
However Jeng teaches wherein the molding member [fig. 1E, substrate 172, para 42] and the conductive post [fig. 1E, conductive via structures 174, para 43] define a trench [fig. 1E, wherein the conductive post fills the trench within the molding member],
wherein the trench includes a first inner surface [annotated fig. 1E] recessed toward the lower package substrate (fig. 1E, substrate 110) from an upper surface of the molding member [annotated fig. 1E] and
a second inner surface [annotated fig. 1E] corresponding to a side surface of the conductive post (fig. 1E, 174),
wherein the side surface of the conductive post [annotated fig. 1E] a extends beyond the first inner surface of the trench in a direction away from the lower package substrate (fig. 1E, 110).
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the conductive post to penetrate through the mold layer to enable stacked dies to communicate directly with the package substrate bypassing lengthy edge wires.
Oh/Jeng fails to explicitly disclose wherein the first inner surface of the molding member includes a first curved surface connecting the upper surface of the molding member to the side surface of the conductive post.
However, Kim teaches in para 38 “upper diameters of the mold via holes 118 a, 118 b, and 118 c are equal to lower diameters thereof and thus inner walls of the mold via holes 118 a, 118 b, and 118 c are vertical. However, the upper diameters may be greater than or less than the lower diameters and thus the inner walls may not be vertical.”
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention the trench to carry a non-vertical curved form factor to relieve mechanical stress, prevent electrical breakdown and ensure defect-free material filling.
PNG
media_image1.png
236
752
media_image1.png
Greyscale
ANNOTATED FIG. 1E
Claims 10-11 & 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Oh et al. (US 2022/0059442) [Hereinafter Oh], Jeng et al. (US 2019/0131284) [Hereinafter Jeng].
Regarding claim 10, Oh teaches A semiconductor package comprising:
a lower package substrate [fig. 9, substrate 500, para 75] including a lower redistribution insulation layer [fig. 9, dielectric layer 101L/201/301/103, para 76] and
a lower redistribution pattern [fig. 9, redistribution patterns 110L/210/310, para 78-80] positioned within the lower redistribution insulation layer (fig. 9, 101L/201/301/103);
a semiconductor chip [fig. 9, semiconductor apparatus 700, para 85] mounted on the lower package substrate (fig. 9, 500);
a connection terminal [fig. 9, connection member 708, para 85] positioned between the lower package substrate (fig. 9, 500) and the semiconductor chip (fig. 9, 700), and connecting the semiconductor chip (fig. 9, 700) to the lower package substrate (fig. 9, 500);
a molding member [fig. 9, molding member 750, para 86] positioned on the lower package substrate (fig. 9, 500) and covering at least a portion of the semiconductor chip (fig. 9, 700); and
a conductive post [fig. 9, mold via 730, para 86] positioned within the molding member (fig. 9, 750) and connected to the lower redistribution pattern [fig. 9, 110L/210/310];
and
an upper package substrate [Oh, fig. 9, substrate 400/600] positioned on the upper surface of the molding member [Oh, fig. 9, 750) and including an upper redistribution insulation layer [Oh, fig. 9, dielectric layer 401, para 87] and including
and
an upper redistribution pattern [Oh, fig. 9, redistribution patter 410, para 87] positioned within the upper redistribution insulation layer (Oh, fig. 9, 401).
Oh fails to explicitly disclose wherein the molding member and the conductive post define a trench,
wherein the trench includes a first inner surface recessed toward a bottom surface of the molding member from the upper surface of the molding member and
a second inner surface corresponding to a side surface of the conductive post, and
wherein the first inner surface of the trench has one of a convex shape and a concave shape.
However Jeng teaches wherein the molding member [fig. 1E, substrate 172, para 42] and the conductive post [fig. 1E, conductive via structures 174, para 43] define a trench [fig. 1E, wherein the conductive post fills the trench within the molding member],
wherein the trench includes a first inner surface [annotated fig. 1E] recessed toward a bottom surface of the molding member (fig. 1E, 172) from the upper surface of the molding member (fig. 1E, 172) and
a second inner surface [annotated fig. 1E] corresponding to a side surface of the conductive post (fig. 1E, 174),
wherein the first inner surface of the trench has one of a convex shape and a concave shape [annotated fig. 1E].
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the conductive post to penetrate through the mold layer to enable stacked dies to communicate directly with the package substrate bypassing lengthy edge wires.
Regarding claim 11, Oh/Jeng teaches The semiconductor package of claim 10,
wherein the second inner surface of the trench of the molding member has a straight line shape [Jeng, annotated fig. 1E].
Regarding claim 17, Oh/Jeng teaches The semiconductor package of claim 10,
wherein the conductive post (Jeng, fig. 1E, 174) is positioned further within the trench of the molding member (Jeng, fig. 1E, 172).
Regarding claim 18, Oh teaches A semiconductor package comprising:
a lower package substrate [fig. 9, substrate 500, para 75] including a lower redistribution insulation layer [fig. 9, dielectric layer 101L/201/301/103, para 76] and
a lower redistribution pattern [fig. 9, redistribution patterns 110L/210/310, para 78-80] positioned within the lower redistribution insulation layer (fig. 9, 101L/201/301/103);
a semiconductor chip [fig. 9, semiconductor apparatus 700, para 85] mounted on the lower package substrate (fig. 9, 500);
a connection terminal [fig. 9, connection member 708, para 85] positioned between the lower package substrate (fig. 9, 500) and the semiconductor chip (fig. 9, 700), and connecting the semiconductor chip (fig. 9, 700) to the lower package substrate (fig. 9, 500);
a molding member [fig. 9, molding member 750, para 86] positioned on the lower package substrate (fig. 9, 500) and covering at least a portion of the semiconductor chip (fig. 9, 700); and
a conductive post [fig. 9, mold via 730, para 86] positioned within the molding member (fig. 9, 750) and connected to the lower redistribution pattern [fig. 9, 110L/210/310];
and
an upper package substrate [Oh, fig. 9, substrate 400/600] positioned on the upper surface of the molding member [Oh, fig. 9, 750) and including an upper redistribution insulation layer [Oh, fig. 9, dielectric layer 401, para 87] and including
and
an upper redistribution pattern [Oh, fig. 9, redistribution patter 410, para 87] positioned within the upper redistribution insulation layer (Oh, fig. 9, 401).
Oh fails to teach wherein the conductive post includes:
a first part positioned on the lower redistribution pattern; and
a second part positioned on the first part and contacting the upper redistribution insulation layer of the upper package substrate,
wherein a width of the first part and a width of the second part are different from each other, and
wherein an upper region of the second part includes a curved surface.
Jeng teaches wherein the conductive post [fig. 1E, via structures 174/conductive layer 179/conductive structure 180, para 44/51] includes:
a first part [annotated fig. 1E-1] positioned on the lower redistribution pattern [fig. 1E, insulating layer 176, para 41]; and
a second part [annotated fig. 1E-1] positioned on the first part [annotated fig. 1E-1] and contacting the upper redistribution insulation layer [fig. 1E, insulating layer 178, para 44] of the upper package substrate,
wherein a width of the first part and a width of the second part are different from each other [annotated fig. 1E-1], and
wherein an upper region of the second part includes a curved surface [annotated fig. 1E-1].
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the conductive post to have varying widths and a curved upper surface to enhance mechanical stability and improve interconnect reliability.
Regarding claim 19, Oh/Jeng teaches The semiconductor package of claim 18,
wherein the width of the first part of the conductive post is greater than the width of the second part [Jeng, annotated fig. 1E-1].
Regarding claim 20 Oh/Jeng teaches The semiconductor package of claim 18,
wherein the width of the first part of the conductive post decreases [Jeng, annotated fig. 1E-1] in a direction toward the lower package substrate [Jeng, fig. 1E, substrate 110, para 27].
PNG
media_image2.png
330
1044
media_image2.png
Greyscale
ANNOTATED FIG. 1E-1
Allowable Subject Matter
Claims 2-9 & 12-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2, Oh/Jeng/Kim The semiconductor package of claim 1, further comprising:
an upper package substrate [Oh, fig. 9, substrate 400/600] positioned on the upper surface of the molding member [Oh, fig. 9, 750) and including an upper redistribution insulation layer [Oh, fig. 9, dielectric layer 401, para 87] and
an upper redistribution pattern [Oh, fig. 9, redistribution patter 410, para 87] positioned within the upper redistribution insulation layer (Oh, fig. 9, 401).
The prior art of record singularly and/or in combination fails to explicitly disclose wherein a first portion of the upper redistribution insulation layer of the upper package substrate is positioned within the trench.
Thereby claim 2 contains allowable subject matter and would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 3 – 9 contain allowable subject matter at least based upon their dependency on claim 2.
Regarding claim 12, Oh/Jeng teaches The semiconductor package of claim 11,
wherein the first portion of the upper redistribution insulation layer [Jeng, fig. 1E, insulating layer 178, para 47] covers the side surface of the conductive post [Jeng, annotated fig. 1E].
The prior of record singular and/or in combination fails to explicitly disclose wherein a first portion of the upper redistribution insulation layer of the upper package substrate is positioned within the trench of the molding member.
Thereby claim 12 contains allowable subject matter in light of the additional limitations recited therein and would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 13 – 16 contain allowable subject matter at least based upon their dependency on claim 12.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FELIX B ANDREWS whose telephone number is (703)756-1074. The examiner can normally be reached Monday - Friday 8:00 am - 5:00 pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/FELIX B ANDREWS/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
Prosecution Insights