DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on how any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 and 5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Taneda (US 2020/0092993 A1).
Regarding Claim 1, Taneda (US 2020/0092993 A1) discloses a printed circuit board (Fig 1-7,11, Table 1) for mounting at least one semiconductor chip device (81; [0131]) thereon, the printed circuit board comprising: a metal structure (20; [0047,0057]) provided in a first area (area about the center of the board; [0138-0142]; note that this area or portion is not structurally limited and thus could encompass the entire board) of the printed circuit board for soldering (90; [0132]) a semiconductor chip device (81) onto the metal structure (20); a main surface (upper surface of 1); and a layer stack (12) comprising: a first layer (122) extending parallel to the main surface, and a second layer (121) extending parallel to the main surface, wherein the first layer (122) is closer to the metal structure (20) than the second layer (121), wherein the first layer (122; [0038-0040]) comprises a first material ([0038-0040]) having a first coefficient of thermal expansion ([0038-0040]) in a lateral direction and the second layer (121; [0034-0036]) comprises a second material ([0034-0036]) having a second coefficient of thermal expansion ([0034-0036]) in the lateral direction such that the printed circuit board is forced by the layer stack into a curved shape ([0138-0142]) at least in the first area of the printed circuit board, wherein the layer stack (12) forces the printed circuit board at room temperature ([0005,0090,0137]) into a convex curvature (see Table 1; Wa is greater than zero) with respect to a view direction from the metal structure (20) to the second layer (121), and wherein the second coefficient of thermal expansion ([0034-0036]) is higher than the first coefficient of thermal expansion ([0038-0040]).
Regarding Claim 5, Taneda further discloses the printed circuit board (Fig 1-7,11) according to claim 1, wherein a ratio of the first coefficient of thermal expansion to the second coefficient of thermal expansion is between 0.3 and 3.5 ([0034-0042]; e.g. 0.53 to 0.8).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2 is rejected under 35 U.S.C. 103 as being unpatentable over Taneda (US 2020/0092993 A1) as applied to claim 1 above and further in view of Kwon (US 2011/0233771 A1).
Regarding Claim 2, Taneda discloses the limitations of the preceding claim.
Taneda further discloses the printed circuit board (Fig 1-7,11) according to claim 1, wherein the layer stack (12) forces the printed circuit board at room temperature into a convex curvature (see Table 1; Wa is greater than zero) with respect to a view direction from the metal structure (20) to the second layer (121).
Taneda does not disclose wherein the layer stack comprises a relative curvature radius change coefficient between 0.01 Meter/K and 0.1 Meter/K at a temperature in a temperature range between 25 degree Celsius and 125 degree Celsius
Kwon teaches of a printed circuit board (Fig 1-6), wherein a layer stack forces the printed circuit board at room temperature ([0066,0070-0079]) into a convex curvature (Fig 1-3) with respect to a view direction from the metal structure to the second layer (structure shown would show a convex curvature if 110 comprised multiple layers).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the board as disclosed by Taneda, wherein the layer stack comprises a relative curvature radius change coefficient between 0.01 Meter/K and 0.1 Meter/K at a temperature in a temperature range between 25 degree Celsius and 125 degree Celsius, in order to control warpage when the board is cool and control coplanarity of solder balls (Kwon, [0060-0079]), since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). Please note that in the instant application, page 8 [0033], Applicant has not disclosed any criticality for the claimed limitations.
Claim(s) 4 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Taneda (US 2020/0092993 A1) as applied to claim 1 above and further in view of Ishida (US 2013/0240258 A1) and Nishio (US 2024/0365477 A1).
Regarding Claim 4, Taneda discloses the limitations of the preceding claim.
Taneda further discloses the printed circuit board (Fig 1-7,11) wherein the second coefficient of thermal expansion ([0034-0042]) is equal to or lower than the first coefficient of thermal expansion.
Taneda does not disclose wherein the first material comprises a first elastic modulus value, wherein the second material comprises a second elastic modulus value, and wherein the second elastic modulus value is higher than the first elastic modulus value at 25 degree Celsius.
Ishida (US 2013/0240258 A1) teaches of a printed circuit board (Fig 1-3,5,7,12,17,18) wherein a second coefficient of thermal expansion is equal ([0042]; e.g. 15 ppm and 15 ppm) to or lower than the first coefficient of thermal expansion, wherein a first material comprises a first elastic modulus value ([0047-0048]), wherein a second material comprises a second elastic modulus value ([0047-0048]), and wherein the second elastic modulus value is higher (e.g. 22 GPa vs. 16 GPa) than the first elastic modulus value.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the board as disclosed by Taneda, wherein the first material comprises a first elastic modulus value, wherein the second material comprises a second elastic modulus value, and wherein the second elastic modulus value is higher than the first elastic modulus value as taught by Ishida, in order to prevent cracking and to control warpage (Ishida, [0045-0048]).
Ishida does not explicitly disclose wherein the second elastic modulus value is higher than the first elastic modulus value at 25 degree Celsius.
Nishio (US 2024/0365477 A1) teaches of a printed circuit board (Fig 1), wherein a first material(17; [0029]) comprises a first elastic modulus value, wherein a second material (16; [0029]) comprises a second elastic modulus value ([0029]), and wherein the second elastic modulus value is higher ([0029,0064]) than a first elastic modulus value at 25 degree Celsius ([0029] “room temperature”).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the board as taught Taneda in view of Ishida, wherein the second elastic modulus value is higher than the first elastic modulus value at 25 degree Celsius as taught by Nishio, in order to prevent connection failure (Nishio, [0004-0008,0072-0076]) and furthermore in order to prevent cracking (Ishida, [0046-0048]).
Regarding Claim 6, Taneda discloses the limitations of the preceding claim.
Taneda does not disclose the printed circuit board according to claim 1 wherein the first material comprises a first elastic modulus value and the second material comprises a second elastic modulus value, and wherein the second elastic modulus value is higher than the first elastic modulus value at 25 degree Celsius.
Ishida (US 2013/0240258 A1) teaches of a printed circuit board (Fig 1-3,5,7,12,17,18) wherein a first material comprises a first elastic modulus value ([0047-0048]) and a second material comprises a second elastic modulus value ([0047-0048]), and wherein the second elastic modulus value is higher (e.g. 22 GPa vs. 16 GPa) than the first elastic modulus value.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the board as disclosed by Taneda, wherein the first material comprises a first elastic modulus value and the second material comprises a second elastic modulus value, and wherein the second elastic modulus value is higher than the first elastic modulus value as taught by Ishida, in order to prevent cracking and to control warpage (Ishida, [0045-0048]).
Ishida does not explicitly disclose wherein the second elastic modulus value is higher than the first elastic modulus value at 25 degree Celsius.
Nishio (US 2024/0365477 A1) teaches of a printed circuit board (Fig 1), wherein a first material(17; [0029]) comprises a first elastic modulus value, wherein a second material (16; [0029]) comprises a second elastic modulus value ([0029]), and wherein the second elastic modulus value is higher ([0029,0064]) than a first elastic modulus value at 25 degree Celsius ([0029] “room temperature”).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the board as taught by Taneda in view of Ishida, wherein the second elastic modulus value is higher than the first elastic modulus value at 25 degree Celsius as taught by Nishio, in order to prevent connection failure (Nishio, [0004-0008,0072-0076]) and furthermore in order to prevent cracking (Ishida, [0046-0048]).
Claim(s) 7 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Taneda (US 2020/0092993 A1) as applied to claim 1 above.
Regarding Claim 7, Taneda discloses the limitations of the preceding claim.
Taneda does not disclose the printed circuit board according to claim 1, wherein the first material comprises a first elastic modulus value which is between 0.5 and 16 GPa at 25 degree Celsius and the first coefficient of thermal expansion is between 10 and 35 ppm/K at 25 degree Celsius, and wherein the second material comprises a second elastic modulus value which is between 6 and 32 GPa at 25 degree Celsius and the second coefficient of thermal expansion is between 14 and 35 ppm/K at 25 degree Celsius .
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the board as disclosed by Taneda, wherein the first material comprises a first elastic modulus value which is between 0.5 and 16 GPa at 25 degree Celsius and the first coefficient of thermal expansion is between 10 and 35 ppm/K at 25 degree Celsius, and wherein the second material comprises a second elastic modulus value which is between 6 and 32 GPa at 25 degree Celsius and the second coefficient of thermal expansion is between 14 and 35 ppm/K at 25 degree Celsius, in order to prevent short-circuiting, prevent cracks or prevent defects, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. Please note that in the instant application, page 9, [0034], Applicant has not disclosed any criticality for the claimed limitations.
Regarding Claim 21, Taneda discloses the limitations of the preceding claim.
Taneda does not disclose the printed circuit board according to claim 1, wherein the first layer comprises a thickness in a range between 60 µm and 200 µm, and wherein the second layer comprises a thickness in the range between 60 µm and 200 µm.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the board as disclosed by Taneda, wherein the first layer comprises a thickness in a range between 60 µm and 200 µm, and wherein the second layer comprises a thickness in the range between 60 µm and 200 µm, in order to control rigidity of the board, minimize and control size of the circuit, control flexibility of the PCB and control short-circuiting between layers by maintaining specific minimum thickness, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Please note that in the instant application, page 9, [0034], Applicant has not disclosed any criticality for the claimed limitations.
Claim(s) 8, 9 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Taneda (US 2020/0092993 A1) as applied to claim 1 above and further in view of Ishida (US 2013/0240258).
Regarding Claim 8, Taneda discloses the limitations of the preceding claim.
Taneda does not disclose the printed circuit board according to claim 1, wherein the layer stack further comprises; a plurality of third layers between the first layer and the second layer, wherein the plurality of third layers comprise a third material having a third coefficient of thermal expansion in the lateral direction, wherein the third coefficient of thermal expansion is lower than the first coefficient of thermal expansion
Ishida (US 2013/0240258) teaches of a printed circuit board (Fig 4), wherein a layer stack further comprises; a plurality of third layers (150,30) between a first layer (50B) and a second layer (50A).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the board as disclosed by Taneda wherein the layer stack further comprises; a plurality of third layers between the first layer and the second layer, as taught by Ishida, in order to control warping, allow the mounting of a high functional chip and increase functionality of the board (Ishida, [0076,0134]) and furthermore increasing layers within the board allows for increasing internal wiring layers and thus increasing potential functional capabilities of the board.
Ishida does not disclose wherein the plurality of third layers comprise a third material having a third coefficient of thermal expansion in the lateral direction, wherein the third coefficient of thermal expansion is lower than the first coefficient of thermal expansion.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the board as taught by Taneda in view of Ishida wherein the layer stack further comprises; a plurality of third layers between the first layer and the second layer, wherein the plurality of third layers comprise a third material having a third coefficient of thermal expansion in the lateral direction, wherein the third coefficient of thermal expansion is lower than the first coefficient of thermal expansion, in order to prevent short-circuiting, prevent cracks and prevent defects (Ishida, [0035-0045]), since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. Please note that in the instant application, page 13, [0054], Applicant has not disclosed any criticality for the claimed limitations.
Regarding Claim 9, Taneda in view of Ishida teaches the limitations of the preceding claim.
Taneda does not explicitly disclose the printed circuit board according to claim 8, wherein the third coefficient of thermal expansion is lower than the second coefficient of thermal expansion.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the board as taught by Taneda in view of Ishida wherein the third coefficient of thermal expansion is lower than the second coefficient of thermal expansion in order to prevent short-circuiting, prevent cracks and prevent defects (Ishida, [0035-0045]), since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. Please note that in the instant application, page 13, [0057], Applicant has not disclosed any criticality for the claimed limitations.
Regarding Claim 22, Taneda discloses the limitations of the preceding claim.
Taneda does not disclose the printed circuit board according to claim 1, wherein the layer stack further comprises: one or more core layers between the first layer and the second layer, wherein each layer of one or more core layers comprises a thickness in a range between 45 µm and 600 µm.
Ishida (US 2013/0240258) teaches of a printed circuit board (Fig 4), wherein a layer stack further comprises; one or more core layers (150,30) between a first layer (50B) and a second layer (50A).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the board as disclosed by Taneda wherein the layer stack further comprises: one or more core layers between the first layer and the second layer as taught by Ishida, in order to control warping, allow the mounting of a high functional chip and increase functionality of the board (Ishida, [0076,0134]) and furthermore increasing layers within the board allows for increasing internal wiring layers and thus increasing potential functional capabilities of the board.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the board as taught by Taneda in view of Ishida, wherein each layer of one or more core layers comprises a thickness in a range between 45 µm and 600 µm, in order to control rigidity of the board, minimize and control size of the circuit, control flexibility of the PCB and control short-circuiting between layers by maintaining specific minimum thickness, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Please note that in the instant application, page 9, [0034], Applicant has not disclosed any criticality for the claimed limitations.
Claim(s) 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Taneda (US 2020/0092993 A1) as applied to claim 1 above and further in view of Hosoda (US 2020/0048420 A1).
Regarding Claim 10, Taneda discloses the limitations of the preceding claim.
Taneda does not explicitly disclose the printed circuit board according to claim 1, wherein the first layer is formed by a low-loss-RF material, the low-loss-RF material having a first loss tangent value of less than 0.1 in a frequency range between 20 GHz and 200 GHz.
Hosoda (US 2020/0048420 A1) teaches of a board ([0186]) wherein a first layer ([0186] “layer”) is formed by a low-loss-RF material ([0150,0186,0241,0296]), the low-loss-RF material having a first loss tangent value of less than 0.1 ([0186]) in a frequency range between 20 GHz ([0186]) and 200 GHz.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the board as taught by Taneda wherein the first layer is formed by a low-loss-RF material, the low-loss-RF material having a first loss tangent value of less than 0.1 in a frequency range between 20 GHz and 200 GHz as taught by Hosoda, in order to provide excellent transmission efficiency (Hosoda, [0186,0253,0273]).
Regarding Claim 11, Taneda in view of Hosoda teaches the limitations of the preceding claim.
Taneda does not explicitly disclose the printed circuit board according to claim 10, wherein the second layer is formed by a material having a second loss tangent value which is higher than the first loss tangent value by a factor of two at a frequency in a range between 20 GHz and 200 GHz.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the board as taught by Taneda in view of Hosoda, wherein the second layer is formed by a material having a second loss tangent value which is higher than the first loss tangent value by a factor of two at a frequency in a range between 20 GHz and 200 GHz, in order to provide excellent transmission efficiency (Hosoda, [0186,0253,0273]), since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. Please note that in the instant application, pages 9-10, [0036], Applicant has not disclosed any criticality for the claimed limitations.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROSHN K VARGHESE whose telephone number is (571)270-7975. The examiner can normally be reached M-Th: 900 am-300 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at 571-272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ROSHN K VARGHESE/ Primary Examiner, Art Unit 2847
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