QFN PACKAGED SEMICONDUCTOR DEVICE AND METHOD OF MAKING THEREOF

§102 §103

DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicants’ election without traverse of Group I, Claims 1-11 in the reply filed on 08/19/2026 is acknowledged. Claims 12-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Claims 1-11 have been fully considered in Examination. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement(s) (IDS) submitted on 06/24/2024 and 11/01/2024 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner. Claim Objections Claims 1, 5, 8-9, and 11 are objected to because of the following informalities: Claim 1, line 1: “A QFN packaged semiconductor device” should read --- A Quad-Flat-No-Leads (QFN) semiconductor device Claim 5, lines 2-3: “the perimeter” should read --- a perimeter --- Claim 8, line 4: “the angle” should read --- an angle --- Claim 8, line 4: “the first side face” should read --- the first side faces --- Claim 9, line 4: “the angle” should read --- an angle --- Claim 9, line 4: “the first side face” should read --- the first side faces --- Claim 11, lines 2-3: “and the first side face is a curved surface” should read --- and each first side face is a curved surface --- Appropriate correction is required. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-5 and 8-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bemmerl (U.S. PG Pub No US2015/0145109A1) Regarding claim 1, Bemmerl teaches a Quad-Flat-No-Leads (QFN) packaged semiconductor device (200) figs. 6A-6B [0054] (fig. 6B shows a QFN package wherein metal contacts are on the bottom 4 edges of the die/package) having a bottom surface (bottom of 210), the QFN packaged semiconductor device (200) comprising: a die pad (214B) fig. 6A [0040, 0050] (pad 214 supporting die/chip [0040, 0054]) on the bottom surface (bottom of 210); a die (212) fig. 6A [0054] (chip) on the die pad (214B); a plurality of leads (214A, 214C) fig. 6A [0054] (may be part of lead frame [0044]) spaced apart from the die pad (214B) and around [0059] a peripheral region [see annotated figs. 6A-6B below] of the bottom surface (bottom of 210); a plurality of bond wires (216) fig. 6A [0054] connecting the die (212) fig. 6A [0054] and the leads (214C), and a molding compound (210) fig. 6A [0027, 0044] (housing formed by molding process) covering the die (212) and the bond wires (216); wherein the QFN packaged semiconductor device (200) has a first thickness (t2) fig. 6A [0056] in a central region (central region) [see annotated figs. 6A-6B below] and a second thickness (t1) fig. 6A [0056] across the peripheral region (peripheral region) [see annotated figs. 6A-6B below], and wherein the second thickness (t1) is less than the first thickness (t2) fig. 6A [0056] (t1 of entire package 200 may be “smaller than” [0056] t2 of entire package 200). [AltContent: connector][AltContent: arrow][AltContent: arrow][AltContent: textbox (TCP)][AltContent: textbox (VT1)][AltContent: arrow][AltContent: textbox (TPP)][AltContent: connector][AltContent: arrow][AltContent: textbox (L2)][AltContent: connector][AltContent: textbox (L1)][AltContent: arrow][AltContent: connector][AltContent: arrow][AltContent: connector][AltContent: arrow][AltContent: arrow][AltContent: ][AltContent: rect][AltContent: connector][AltContent: connector][AltContent: textbox (Peripheral region outside of central region )][AltContent: textbox (Central region)] PNG media_image1.png 935 933 media_image1.png Greyscale Annotated figs. 6A-6B Regarding claim 2, Bemmerl teaches the QFN packaged semiconductor device (200) figs. 6A-6B [0054] according to claim 1. Bemmerl also teaches wherein the peripheral region (laterally) surrounds the central region (see annotated fig. 6B above). Regarding claim 3, Bemmerl teaches the QFN packaged semiconductor device (200) figs. 6A-6B [0054] according to claim 1. Bemmerl also teaches wherein a thickness (TCP) [see annotated fig. 6A above] of the molding compound (210) fig. 6A [0027, 0044] (housing formed by molding process) in the central region (at the peripheral edge of central region bordering peripheral region) is in a range between 0.7 and 3 times (~1.0 times / equal to) a thickness (TPP) [see annotated fig. 6A above] of the molding compound (210) fig. 6A [0027, 0044] in the peripheral region (a thickness TCP of molding compound 210 at the central region periphery bordering the peripheral region is defined as nearly equivalent to a thickness TPP of 210 at the peripheral region periphery bordering the central region, since they are both portions of the molding compound 210 at nearly the same location – see annotated fig. 6A above). Regarding claim 4, Bemmerl teaches the QFN packaged semiconductor device (200) figs. 6A-6B [0054] according to claim 1. Bemmerl also teaches wherein the central region (central region) [see annotated fig. 6A-6B above] extends (vertically) beyond a (top) perimeter of the die (212) fig. 6A [0054] (chip) by a distance (VT1) which is in a range between 0.7 and 1.3 times (defined as equal to / 1.0 times) a thickness (VT1) of the molding compound (210) fig. 6A [0027, 0044] in the central region (the central region comprising the mold compound 210 above the die 212 extends by a vertical distance VT1 equal to a thickness VT1 of the mold compound 210 at location of 210 overlapping the die 212, as defined in annotated figs. 6A-6B above). Regarding claim 5, Bemmerl teaches the QFN packaged semiconductor device (200) figs. 6A-6B [0054] according to claim 1. Bemmerl also teaches wherein the peripheral region [see annotated figs. 6A-6B above] extends inwards from a perimeter of the device (200) (perimeter of 200 from through hole 222A inwards [0053]) by a distance (L2) [see annotated figs. 6A-6B above] which is in a range between 1 and 1.3 times (L2 defined as slightly greater than 1.0 times, and clearly less than 1.3 times, L1) (see annotated figs. 6A-6B above) an exposed length (L1) of the leads (214A, 214C) fig. 6A [0054] on the bottom surface (peripheral region extends a distance L2 inwards from edge of lead 214 through midsection of lead 214, which is approximately equal to and slightly greater than L1, a length of bottom of 214). [AltContent: ][AltContent: textbox (Central Region )]Regarding claim 8, Bemmerl teaches the QFN packaged semiconductor device (200) figs. 6A-6B [0054] according to claim 1. Bemmerl also teaches wherein the central region (central region comprising molding compound 210) [0027, 0044] (see annotated fig. 6A-II below) has (comprises) a first top surface (T1 of 210) (see annotated fig. 6A-II below) and first (inner) side faces (S1-I, S1-II of 210) (see annotated fig. 6A-II below), the peripheral region has (comprises) a second top surface (T2 of 210) (see annotated fig. 6A-II below) and second side faces (S2-I, S2-II of 210) (see annotated fig. 6A-II below), and an angle between the second top surface (T2) and the first side faces (including S1-I) is a right angle (inner side faces S1-I, S1-II are defined as vertically oriented, while local top surface T2 is horizontally oriented, such that they form a right angle with one another, as defined in annotated fig. 6A-II below). [AltContent: arrow][AltContent: textbox (Right angle )][AltContent: rect][AltContent: connector][AltContent: connector][AltContent: arrow][AltContent: arrow][AltContent: textbox (S1-I)][AltContent: textbox (S1-II)][AltContent: oval][AltContent: oval][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: textbox (S1-II)][AltContent: textbox (S2-II)][AltContent: arrow][AltContent: textbox (T2)][AltContent: textbox (T1)][AltContent: textbox (Peripheral Region )][AltContent: textbox (Peripheral Region )][AltContent: connector][AltContent: connector] PNG media_image2.png 418 886 media_image2.png Greyscale Annotated fig. 6A-II of Bemmerl Regarding claim 9, Bemmerl teaches the QFN packaged semiconductor device (200) figs. 6A-6B [0054] according to claim 1. Bemmerl also teaches wherein the central region (central region comprising molding compound 210) [0027, 0044] (see annotated fig. 6A-III below) has (comprises) a first top surface (T1 of 210) (see annotated fig. 6A-III below) and first side faces (S1-I, S1-II of 210) (see annotated fig. 6A-III below), the peripheral region has (comprises) a second top surface (T2 of 210) (see annotated fig. 6A-III below) and second side faces (S2-I, S2-II of 210) (see annotated fig. 6A-III below), and an angle between the second top surface (T2) and the first side faces (including S1-I) is an obtuse angle (outer side faces S1-I, S1-II are defined as slanted, while local top surface T2 is horizontally oriented, such that they form an obtuse angle (greater than 90 degrees) with one another, as defined in annotated fig. 6A-III below). [AltContent: arrow][AltContent: textbox (Obtuse angle )][AltContent: arrow][AltContent: textbox (T2)][AltContent: arc][AltContent: arrow][AltContent: arrow][AltContent: textbox (S1-I)][AltContent: textbox (S1-II)][AltContent: arrow][AltContent: textbox (T1)][AltContent: arrow][AltContent: arrow][AltContent: textbox (S2-I)][AltContent: textbox (S2-II)] PNG media_image3.png 489 985 media_image3.png Greyscale Annotated fig. 6A-III of Bemmerl Regarding claim 10, Bemmerl teaches the QFN packaged semiconductor device (200) figs. 6A-6B [0054] according to claim 1. Bemmerl also teaches wherein the central region (central region comprising molding compound 210) [0027, 0044] (see annotated fig. 6A above) has first side faces (uppermost and lowermost side surface of 210 in central region) [see annotated fig. 6A above], and each first side face (uppermost and lowermost side surface of 210) is a flat surface. Regarding claim 11, Bemmerl teaches the QFN packaged semiconductor device (200) figs. 6A-6B [0054] according to claim 1. Bemmerl also teaches wherein the central region (central region comprising molding compound 210) [0027, 0044] (see annotated fig. 6A-IV above) has first side faces (LS1, RS1 of 210) (see annotated fig. 6A-IV above), and each first side face (LS1, RS1 of 210) is a curved surface (respective borders of 210 (LS1, RS1) with leads 214A, 214C are curved surfaces– see annotated fig. 6A-IV below). [AltContent: oval][AltContent: arrow][AltContent: arrow][AltContent: oval][AltContent: textbox (RS1)][AltContent: textbox (LS1)] PNG media_image3.png 489 985 media_image3.png Greyscale Annotated fig. 6A-IV of Bemmerl Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Bemmerl (U.S. PG Pub No US2015/0145109A1), as applied in claim 1 above, in view of Koduri (U.S. PG Pub No US2022/0230944A1). Regarding claim 6, Bemmerl teaches QFN packaged semiconductor device (200) figs. 6A-6B [0054] according to claim 1. However, Bemmerl does not explicitly disclose wherein a thickness of the peripheral region (comprising leftmost/rightmost surfaces of molding compound 210) fig. 6A [0054] is in a range between 0.2 and 0.6mm (insufficient size information). Koduri teaches a QFN packaged semiconductor device [see fig. 15A, 0046, 0131-0133] wherein a thickness of the peripheral region (comprising leftmost/rightmost surfaces of encapsulating/molding compound 112) fig. 15A [0131-0133] is in a range between 0.2 and 0.6mm (thickness may be 0.05mm to 1 mm – encompassing the claimed range). While Koduri does not explicitly disclose a thickness of the peripheral region defined by the thickness of the molding compound as in the range 0.2 and 0.6 mm, [0131] of Koduri discloses that the thickness of the molding compound may be 0.05mm to 1 mm. These ranges overlap. Therefore, in the absence of evidence of criticality for the narrower range, one of ordinary skill in the art would consider the disclosed range to be sufficiently within the scope of the teachings of Koduri [0131-0133]. (See MPEP 2144.05, I). Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the mold compound of the peripheral region of Bemmerl to have a thickness on the order of tenths of millimeters [0131] in order to ensure an optimal degree of encapsulation of QFN components [0131] for structural stability [0131] and moisture protection [0131], according to art recognized parameters [0131-0133], as taught by Bemmerl. Regarding claim 7, Bemmerl teaches the QFN packaged semiconductor device (200) figs. 6A-6B [0054] according to claim 1. However, Bemmerl does not explicitly disclose wherein the central region (comprising portion of molding compound 210 overlapping leads die 212) fig. 6A [0054] has a first top surface (uppermost surface of 210), and a distance from the first top surface (uppermost surface of 210) to a top surface of the die (212) fig. 6A [0054] is in a range between 0.4 and 0.7 mm (insufficient size information). Koduri teaches a QFN packaged semiconductor device [see fig. 15A, 0046, 0131-0133] wherein the central region (comprising portion of molding compound 112 overlapping leads die f) fig. 15A [0131, 0133] has a first top surface (uppermost surface of 112), and a distance from the first top surface (uppermost surface of 112) to a top surface of the die (f/106) fig. 15A [0133] is in a range between 0.4 and 0.7 mm (distance equal to total thickness of molding compound 112 minus combined thickness of die attach 104 and die 106 [0131-0133]; thickness of molding compound 112 may be 0.05mm to 1 mm [0131] while die attach is 0.025mm and die is 0.200 mm (combined thickness of 0.225 mm); therefore, claimed condition of between 0.4mm and 0.7mm is met when thickness of entirety molding compound 112 is between 0.625 mm and 0.925mm [0131, 0133 Koduri]). While Koduri does not explicitly disclose a thickness of the peripheral region defined by the thickness of the molding compound as in the range 0.625 and 0.925 mm, [0131] of Koduri discloses that the thickness of the molding compound may be 0.05mm to 1 mm. These ranges overlap. Therefore, in the absence of evidence of criticality for the narrower range, one of ordinary skill in the art would consider the disclosed range to be sufficiently within the scope of the teachings of Koduri [0131-0133]. (See MPEP 2144.05, I). Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the mold compound Bemmerl to have a thickness on the order of tenths of millimeters [0131] in order to ensure an optimal degree of encapsulation of QFN components [0131] for structural stability [0131] and moisture protection [0131], as taught by Koduri. Further, Koduri evidences art recognized suitable parameters for the thicknesses of the molding compound, die, and die attach material [0131, 0133]. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Remaining references made available on the PTO-892 form are each considered relevant to the present disclosure because they all feature QFN packages with molding compounds and dies having various thicknesses. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEAN AYERS WINTERS whose telephone number is (571)270-3308. The examiner can normally be reached Monday - Friday 10:30 am - 7:00 pm (EST). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SEAN AYERS WINTERS/Examiner, Art Unit 2892 10/02/2026 /NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892