Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of claim(s) to be treated in this office action:
a. Independent: 1, 13 and 16
b. Pending: 1-8, 10-17, 19-20
Claims 1, 13 and 16 have been amended and claims 9 and 18 are withdrawn.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Specification
The new title is reviewed and accepted.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 and 5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lekkala et al. (US 11043948).
Regarding independent claim 1, Lekkala discloses an apparatus (Fig. 4), comprising:
first and second input transistors of a first type (Fig. 4 shows nmos input transistors 110 and 112), gate nodes of the first and second input transistors coupled to first and second inputs (Fig. 4 shows two gates are connected to 101 and 102 respectively), respectively;
first and second load transistors of a second type (Fig. 4 shows pmos load transistors 120 and 122) coupled to the first and second input transistors in series, respectively (Fig. 4 shows series connection between corresponding input transistor and load transistor), the first input transistor and first load transistor coupled to a first output (Fig. 4 and (14) describes output node 219), the second input transistor and second load transistor coupled to a second output (Fig. 4 shows similar connection on the right side for transistors 112 and 122);
at least one resistor coupled to gate nodes of the first and second load transistors (Fig. 4 shows resistors 220 and 222 connected to gates of the load transistors), wherein the gate node of the first load transistor and the gate node of the second load transistor are different nodes and are separately coupled to a bias voltage through the at least one resistor (Fig. 4 shows gate nodes of the two load transistors are different and are electrically coupled to VCCA);
a first capacitive device coupled to the first input and to the gate node of the first load transistor (Fig. 4 shows capacitor 410 connected between input 101 and gate node of load transistor 120); and
a second capacitive device coupled to the second input and to the gate node of the second load transistor (Fig. 4 shows capacitor 412 connected between input 102 and gate node of load transistor 122).
Regarding claim 2, Lekkala discloses all the elements of claim 1 as above and further the first and second capacitive devices comprise capacitors (Fig. 4).
Regarding claim 5, Lekkala discloses all the elements of claim 1 as above and further the first capacitive device is coupled to the gate node of the first input transistor and to the gate node of the first load transistor, and the second capacitive device is coupled to the gate node of the second input transistor and to the gate node of the second load transistor (Fig. 4 shows the prescribed connections).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8 and 10-12 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lekkala et al. (US 11043948) in view of Kollmann (US 20060049884).
Regarding claim 8, Lekkala discloses all the elements of claim 1 as above and through Kollmann further the input transistors of the first type comprise PMOS transistors (Figs. 8-9 shows 38 and 39 as pmos transistors), and the load transistors of the second type comprise NMOS transistors (Figs. 8-9 shows 46 and 47 as nmos transistors).
Regarding claim 10, Lekkala discloses all the elements of claim 1 as above and through Kollmann further the apparatus includes a clock input buffer, the clock input buffer including the first and second input transistors, the first and second load transistors, the at least one resistor (Figs. 8-9 and [0013]), and
Lekkala teaches the first and second capacitive devices and configured to receive external clock signals at the first and second inputs and output internal clock signals at the first and second outputs (Fig. 4 and (21)).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Kollmann to Lekkala in order to provide with an oscillator circuit that has a simple structure and enables operation that is at least largely non-susceptible to interference as taught by Kollmann ([0007]).
Regarding claim 11, Lekkala and Kollmann together disclose all the elements of claim 10 as above and through Kollmann further the clock input buffer is a differential amplifier ([0037]-[0040] describes input stage designed as a differential amplifier).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Kollmann to modified Lekkala in order to provide with an oscillator circuit that has a simple structure and enables operation that is at least largely non-susceptible to interference as taught by Kollmann ([0007]).
Regarding claim 12, Lekkala discloses all the elements of claim 1 as above and through Kollmann further a bias voltage generator configured to generate the bias voltage (Fig. 4 shows current source 54 to provide bias current. Here examiner asserts that current and voltage are interchangeable).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Kollmann to Lekkala in order to provide with an oscillator circuit that has a simple structure and enables operation that is at least largely non-susceptible to interference as taught by Kollmann ([0007]).
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Lekkala et al. (US 11043948) in view of Otori et al. (US 20020118587).
Regarding claim 3, Lekkala discloses all the elements of claim 1 as above and through Otori further the first and second capacitive devices comprise MIS transistors ([0061] describes MIS transistors for capacitive elements).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Otori to Lekkala in order to improve the reliability of long-term data retention as taught by Otori ([0007]).
Regarding claim 4, Lekkala discloses all the elements of claim 1 as above and through Otori further the first and second capacitive devices comprise low threshold voltage MOS transistors ([0061] describes low threshold voltage MOS transistors).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Otori to Lekkala in order to improve the reliability of long-term data retention as taught by Otori ([0007]).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Lekkala et al. (US 11043948) in view of Konishi et al. (JP 2010087284).
Regarding claim 6, Lekkala discloses all the elements of claim 1 as above and through Konishi further the at least one resistor comprises a plurality of resistors coupled in series between the gate nodes of the first and second load transistors (pg.: 11 describes a resistance circuit including a plurality of resistance elements).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Konishi to Lekkala in order to simplify the manufacturing process and reduce the manufacturing cost as taught by Konishi (TECH-PROBLEM).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Lekkala et al. (US 11043948) in view of Konishi et al. (JP 2010087284) and Kollmann (US 20060049884).
Regarding claim 7, Lekkala and Konishi together disclose all the elements of claim 6 as above and through Kollmann further a common node of the series-coupled resistors is coupled to the bias voltage (Figs. 8-9).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Kollmann to modified Lekkala in order to provide with an oscillator circuit that has a simple structure and enables operation that is at least largely non-susceptible to interference as taught by Kollmann ([0007]).
Applicant stated on Remarks submitted on 2/2/2026 that all independent claims 1, 13 and 16 encompass either same or substantially same claim features drawn in Figs. 3A-3B, 7A-7B and 8A-8B.
Therefore, claims 13-17 and 19-20 are rejected by same way as claims 1-8 and 10-12.
Response to Arguments
Applicant’s arguments with respect to independent claims have been considered but are moot because the new ground of rejection rely on previously used references but applied in a different fashion.
Rejections are maintained at-least for above mentioned reasons. Details will be found under “Claim Rejections”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SULTANA BEGUM/Primary Examiner, Art Unit 2824 6/9/2026
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