Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of claim(s) to be treated in this office action:
a. Independent: 1, 13 and 16
b. Pending: 1-8, 10-17, 19-20
Claims 9 and 18 are withdrawn.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Election/Restrictions
Claims 9 and 18 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species. Election was made without traverse in the reply filed on 2/2/2026.
Information Disclosure Statement
No information disclosure statement has been filed.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Clock input buffer with capacitive device coupled between input node and gate node of load transistor.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5, 8, 10-12, 13-17 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kollmann (US 20060049884) in view of Lekkala et al. (US 11043948).
Regarding independent claim 1, Kollmann discloses an apparatus (Figs. 8-9), comprising:
first and second input transistors of a first type, gate nodes of the first and second input transistors coupled to first and second inputs, respectively (Figs. 8-9 shows two transistors 38 and 39, gates of those transistors are connected to two inputs 12 and 13 respectively);
first and second load transistors of a second type coupled to the first and second input transistors in series, respectively (Figs. 8-9 shows two load transistors 46 and 47 connected to transistors 38 and 39 in series respectively), the first input transistor and first load transistor coupled to a first output, the second input transistor and second load transistor coupled to a second output (Figs. 8-9 shows with arrow 27 two outputs);
at least one resistor coupled to gate nodes of the first and second load transistors, the gate nodes of the first and second load transistors coupled to a bias voltage through the at least one resistor (Figs. 8-9 shows that transistor 55 is diode connected, which acts as a resistor. Also, current source 54 is connected to diode connected transistor 55. Here examiner asserts that current and voltage are interchangeable);
Kollmann does not show a first capacitive device coupled to the first input and to the gate node of the first load transistor; and
a second capacitive device coupled to the second input and to the gate node of the second load transistor.
However, Lekkala teaches a first capacitive device coupled to the first input and to the gate node of the first load transistor (Fig. 4 shows capacitor 410 is coupled directly between the gate of the input transistor 110 and the gate of the load transistor 120); and
a second capacitive device coupled to the second input and to the gate node of the second load transistor (Fig. 4 shows capacitor 412 is coupled directly between the gate of the input transistor 112 and the gate of the load transistor 122).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Lekkala to Kollmann in order to provide improved high frequency differential amplifier as taught by Lekkala (Fig. 4 and (4)).
Regarding claim 2, Kollmann and Lekkala together disclose all the elements of claim 1 as above and through Lekkala further the first and second capacitive devices comprise capacitors (Fig. 4).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Lekkala to modified Kollmann in order to provide improved high frequency differential amplifier as taught by Lekkala (Fig. 4 and (4)).
Regarding claim 5, Kollmann and Lekkala together disclose all the elements of claim 1 as above and through Lekkala further the first capacitive device is coupled to the gate node of the first input transistor and to the gate node of the first load transistor, and the second capacitive device is coupled to the gate node of the second input transistor and to the gate node of the second load transistor (Fig. 4 shows the prescribed connections).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Lekkala to modified Kollmann in order to provide improved high frequency differential amplifier as taught by Lekkala (Fig. 4 and (4)).
Regarding claim 8, Kollmann and Lekkala together disclose all the elements of claim 1 as above and through Kollmann further the input transistors of the first type comprise PMOS transistors (Figs. 8-9 shows 38 and 39 as pmos transistors), and the load transistors of the second type comprise NMOS transistors (Figs. 8-9 shows 46 and 47 as nmos transistors).
Regarding claim 10, Kollmann and Lekkala together disclose all the elements of claim 1 as above and through Kollmann further the apparatus includes a clock input buffer, the clock input buffer including the first and second input transistors, the first and second load transistors, the at least one resistor (Figs. 8-9 and [0013]), and
Lekkala teaches the first and second capacitive devices and configured to receive external clock signals at the first and second inputs and output internal clock signals at the first and second outputs (Fig. 4 and (21)).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Lekkala to modified Kollmann in order to provide improved high frequency differential amplifier as taught by Lekkala (Fig. 4 and (4)).
Regarding claim 11, Kollmann and Lekkala together disclose all the elements of claim 10 as above and through Kollmann further the clock input buffer is a differential amplifier ([0037]-[0040] describes input stage designed as a differential amplifier).
Regarding claim 12, Kollmann and Lekkala together disclose all the elements of claim 1 as above and through Kollmann further a bias voltage generator configured to generate the bias voltage (Fig. 4 shows current source 54 to provide bias current. Here examiner asserts that current and voltage are interchangeable).
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Kollmann (US 20060049884) in view of Lekkala et al. (US 11043948) and Otori et al. (US 20020118587).
Regarding claim 3, Kollmann and Lekkala together disclose all the elements of claim 1 as above and through Otori further the first and second capacitive devices comprise MIS transistors ([0061] describes MIS transistors for capacitive elements).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Otori to modified Kollmann in order to improve the reliability of long-term data retention as taught by Otori ([0007]).
Regarding claim 4, Kollmann and Lekkala together disclose all the elements of claim 1 as above and through Otori further the first and second capacitive devices comprise low threshold voltage MOS transistors ([0061] describes low threshold voltage MOS transistors).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Otori to modified Kollmann in order to improve the reliability of long-term data retention as taught by Otori ([0007]).
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Kollmann (US 20060049884) in view of Lekkala et al. (US 11043948) and Konishi et al. (JP 2010087284).
Regarding claim 6, Kollmann and Lekkala together disclose all the elements of claim 1 as above and through Konishi further the at least one resistor comprises a plurality of resistors coupled in series between the gate nodes of the first and second load transistors (pg: 11 describes a resistance circuit including a plurality of resistance elements).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Konishi to modified Kollmann in order to simplify the manufacturing process and reduce the manufacturing cost as taught by Konishi (TECH-PROBLEM).
Regarding claim 7, Kollmann, Lekkala and Konishi together disclose all the elements of claim 6 as above and through Kollmann further a common node of the series-coupled resistors is coupled to the bias voltage (Figs. 8-9).
Applicant stated on Remarks submitted on 2/2/2026 that all independent claims 1, 13 and 16 encompass either same or substantially same claim features drawn in Figs. 3A-3B, 7A-7B and 8A-8B.
Therefore, claims 13-17 and 19-20 are rejected by same way as claims 1-8 and 10-12.
Conclusion
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/SULTANA BEGUM/Primary Examiner, Art Unit 2824 2/20/2026