DETAILED ACTION
This action is responsive to the claims filed 30 Mary 2024. Claims 1-21 are pending. Claim 1 is independent. Claims 12-21 have been Withdrawn under a restriction.
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restriction
In the letter dated 30 Mar 2026, the applicant elected claims 1-11 for examination.
Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claims 12-21 have been withdrawn pending further action. Applicant is thanked for understanding that Species 3 included claims 18-21.
Examiner Note
The present application has used the limitation of “first and second track” and “section of the track”. The limitations “track” and “section of the track” are not used anywhere in applicant’s specification. Based only upon the original claims, a “track” could be interpreted as a comprising of any circuit, or plurality of lines, or even a single line. Further limitation to the definition or claims of a “track” may be seen as “new material”.
Allowable Subject Matter
Claims 6 – 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections – 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless —
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1 – 5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee, G., U.S. Patent Application Publication 2020/0294563 (“Lee”).
Regarding claim 1, Lee teaches:
An apparatus comprising: first and second tracks extending in parallel with each other; (Lee, fig 3, 8, “[0123] FIG. 8 illustrates a configuration of a semiconductor apparatus 204 related to a read operation. [0122] Since the first data lines 200 and the control signal lines 300 and 301 are designed symmetrically with respect to the plurality of memory banks BK0 and BKn, the data transfer time difference and the control signal transfer time difference may be equalized to the same value during the write operation.”; a memory apparatus with multiple memory banks with multiple control signals used in a memory read operation; that the control lines 300 and 301 are “symmetrical” with data lines; that the control lines are symmetrical with “Write enable” line to the “switching circuits 400”; therefore the signals WE, 300, 301, and data signals 200 run at least in a parallel fashion from one end of the memory apparatus memory bank “0” to memory bank “n”).
a first circuit configured to activate a first control signal; (Lee, fig 3, 8, “[0128] Since a write enable signal WE is at a low level during the read operation, the plurality of switching circuits 400 may couple the second control signal lines 301 to the plurality of memory banks BK0 to BKn-1.”; a control line “Write Enable” (i.e. claimed first circuit and first control signal) which is at a low level for a read operation (WE) first control signal sent on “first circuit” to each mem bank and each switch circ 400).
a second circuit configured to activate a first timing signal after receiving the first control signal; (Lee, fig 3, 8, “[0125] The control signal lines 300 and 301 may be divided into first control signal lines 300 and second control signal lines 301. The first control signal lines 300 may be extended from the peripheral circuit region 102 to the memory bank BKn which is the farthest from the peripheral circuit region 102,”; a “second circuit” comprising peripheral circuit region 102, all of the “switching circuit 400” associated with each memory bank, and inclusive of signal lines 300 of fig 8; a (i.e. first timing signal) activated on signal line 300).
a third circuit configured to receive the first timing signal from the second control circuit and return back the first timing signal to the second control circuit; (Lee, fig 3, 8, “[0125] The control signal lines 300 and 301… and the second control signal lines 301 may diverge from the first control signal lines 300 of the memory bank BKn side to be extended toward the memory bank BK0 which is the closest to the peripheral circuit region 102.”; a “third circuit” comprising a signal line 301 which is returned to each of the “switching circuit 400” of the “second circuit” and returns the signal line 301 to the “switching circuit 400” of each memory bank).
a first signal line conveying the first control signal from the first circuit to the second circuit; (Lee, fig 3, 8, “[0128] Since a write enable signal WE is at a low level during the read operation, the plurality of switching circuits 400 may couple the second control signal lines 301 to the plurality of memory banks BK0 to BKn-1.”; WE sent to each “switching circuit 400” of each memory bank; the switching circuits 400 are part of the claimed “second circuit”).
a second signal line conveying the first timing signal from the second circuit to the third circuit; and (Lee, fig 3, 8, “[0125] The control signal lines 300 and 301 may be divided into first control signal lines 300 and second control signal lines 301. The first control signal lines 300 may be extended from the peripheral circuit region 102 to the memory bank BKn which is the farthest from the peripheral circuit region 102,”; a “second circuit” comprising peripheral circuit region 102, all of the “switching circuit 400” associated with each memory bank; signal line 300 transmits the timing as shown in fig 8).
a third signal line conveying the first timing signal from the third circuit to the second circuit, (Lee, fig 3, 8, “[0125] The control signal lines 300 and 301… and the second control signal lines 301 may diverge from the first control signal lines 300 of the memory bank BKn side to be extended toward the memory bank BK0 which is the closest to the peripheral circuit region 102.”; a “third circuit” comprising a signal line 301 which is returned to each of the “switching circuit 400” of the “second circuit”).
wherein the first signal line is provided on a first section of the first track, (Lee, fig 3, 8, “[0128] Since a write enable signal WE is at a low level during the read operation, the plurality of switching circuits 400 may couple the second control signal lines 301 to the plurality of memory banks BK0 to BKn-1.”; a control line “Write Enable” which is at a low level for a read operation (WE) first control signal sent on “first circuit” to each mem bank and each switch circ 400; the signal line WE has been interpreted as a “first section” of a “first track”; the “first section” is only limited as a signal line carrying the “first signal line” and “parallel” to the second track).
wherein the second signal line is provided on one of a second section of the first track and a first section of the second track, and (Lee, fig 3, 8, “[0125] The control signal lines 300 and 301 may be divided into first control signal lines 300 and second control signal lines 301. The first control signal lines 300 may be extended from the peripheral circuit region 102 to the memory bank BKn which is the farthest from the peripheral circuit region 102,”; a “second circuit” comprising peripheral circuit region 102, all of the “switching circuit 400” associated with each memory bank; signal line 300 transmits the timing as shown in fig 8; the signal lines 300 have been interpreted as a “second section of the first track” that carries the second signal and runs parallel to the first section of first track).
wherein the third signal line is provided on the other of the second section of the first track and the first section of the second track (Lee, fig 3, 8, “[0125] The control signal lines 300 and 301… and the second control signal lines 301 may diverge from the first control signal lines 300 of the memory bank BKn side to be extended toward the memory bank BK0 which is the closest to the peripheral circuit region 102.”; a “third circuit” comprising a signal line 301 which is returned to each of the “switching circuit 400” of the “second circuit”; the signal line 301 has been interpreted as “the first section of the second track”).
Regarding claim 2, Lee teaches The apparatus of claim 1, further comprising a first memory cell array, wherein the first circuit is configured to activate the first control signal responsive to a first external command that instructs a read operation to the first memory cell array. (Lee, fig 3, 8, “[0043] The switching circuit 400 may couple the first control signal lines 300 to the first memory bank BK0 when the write enable signal WE is at a high level, and couple the second control signal lines 301 to the first memory bank BK0 when the write enable signal WE is at a low level.”; a first memory bank BK0, that is either activated for a write operation or for a read operation based on the enable signal WE signal (i.e. claimed first signal line carrying the first control signal)).
Regarding claim 3, Lee teaches The apparatus of claim 2, wherein the first memory cell array is configured to start an output operation of a read data responsive to the first control signal. (Lee, fig 3, 8, “[0127] The semiconductor apparatus 204 in accordance with an embodiment may equalize to the same value a difference between times required for transferring control signals, i.e. a command strobe signal CMDP and an address signal ADD, to the plurality of memory banks BK0 to BKn and a difference between times required for transferring a plurality of output data RGIO_BK0 to RGIO_BKn to the peripheral circuit region 102, through the above-described control signal lines 300 and 301.”; a plurality of output data RGIO_BK0 that is started based on the signals WE, 300 and 301).
Regarding claim 4, Lee teaches The apparatus of claim 3, wherein the first timing signal is activated at substantially the same timing when the first memory cell array finishes outputting the read data to a fourth circuit. (Lee, fig 3, 6, 8, “[0107] An example in which sequential read operations for BKl-BKl-BK0-BKl-BK0-BK0 are performed will be described with reference to FIG. 6. [0120] That is, the command strobe signal CMDP and the address signal ADD may be sequentially transferred to the plurality of memory banks BK0-BKl, … , -BKn-1-BKn from the closest memory bank to the peripheral circuit region 102 to the farthest memory bank from the peripheral circuit region 102. [0129] That is, the command strobe signal CMDP and the address signal ADD may be sequentially transferred to the plurality of memory banks BKn-BKn-1, … , -BKl-BK0 from the farthest memory bank from the peripheral circuit region 102 to the closest memory bank to the peripheral circuit region 102.”; that data can be read sequentially, or one after the other, from each of the memory banks using the output circuitry and multiplexors).
Regarding claim 5, Lee teaches The apparatus of claim 4, further comprising a data bus, wherein the fourth circuit is configured to transfer the read data to the data bus responsive to the first timing signal passed through the third and second circuits. (Lee, fig 3, 8, “[0124] Referring to fig 8, … the semiconductor apparatus 204 includes a plurality of memory banks BK0 to BKn, a plurality of switching circuits 400, a plurality of multiplexers 500 and a plurality of sorting control signal summation circuit 600.”; an output bus (i.e. fourth circuit) that takes timing signals RGIO and PINSUM, uses multiplexors, and outputs data based on the input timing signals).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DONALD H.B. BRASWELL whose telephone number is (469)295-9119. The examiner can normally be reached on 7-5 Central Time (Dallas).
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/Donald HB Braswell/ Primary Examiner, Art Unit 2825
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