Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Claim Objections
Claims 1-11 are objected to because of the following informalities:
Claim 1 presently recites the limitation “the idle state” in line 5. There is insufficient antecedent basis for this limitation in the claim.
For the purpose of the examination, the term “the idle state” will be treated as “an idle state.”
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Miura et al. (US Pub # 2005/0232059).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding independent claim 1, Miura et al. teach an apparatus, comprising: a memory device; and a bias temperature instability (BTI) controller configured to generate and output a command and address signal for memory testing (see Fig. 2-3, 6-8, 17, 20, 22-30, 36-40 and paragraph 0080-0093, 0109-0114, 0135-0140, 0168-0183, 0202-0204, 0255-0262 where memory device includes CTL_LOGIC controller where COM_GEN unit generate command and A_CONT unit generate address signal) wherein the command and address signal causes the memory device in the idle state to operate for the testing (see Fig. 2-3, 6-8, 17, 20, 22-30, 36-40 and paragraph 0080-0093, 0109-0114, 0135-0140, 0168-0183, 0202-0204, 0255-0262, see specially Fig.8 step 1-3 where idle state for read write testing).
Even though Miura et al. teach controller CTL_LOGIC unit including command and address generator, temperature measuring unit TMP but silent exclusively about a bias temperature instability (BTI) controller. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Miura et al. where temperature module of controller including command and address generator with idle state operation function as a bias temperature instability (BTI) controller in order to reduce data retention power and to improve speed and reliability of memory device (see paragraph 0221, 0223).
Regarding claim 2, Miura et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Miura et al. further teach, wherein the command and address signal is supplied to a command and address control circuit of the memory device to cause the command and address control circuit to generate an output signal for a memory bank logic circuit (see Fig. 2-3, 6-8, 17, 20, 22-30, 36-40 and paragraph 0080-0093, 0109-0114, 0135-0140, 0168-0183, 0202-0204).
Regarding claim 3, Miura et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Miura et al. further teach, wherein the command and address signal is supplied to a command and address control circuit of the memory device which translates command and address information from the command and address signal (see Fig. 2-3, 6-8, 17, 20, 22-30, 36-40 and paragraph 0080-0093, 0109-0114, 0135-0140, 0168-0183, 0202-0203).
Regarding claim 4, Miura et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Miura et al. further teach, further comprising an oscillator configured to generate a clock signal, wherein the BTI controller generates the command and address signal having command and address transition timings aligned with the clock signal (see Fig. 2-3, 6-8, 17, 20, 22-30, 36-40 and paragraph 0080-0093, 0109-0114, 0135-0140, 0168-0183, 0202-0204, 0255).
Regarding claim 5, Miura et al. teach all claimed subject matter as applied in prior rejection of claim 4 on which this claim depends.
Miura et al. further teach, wherein the clock signal is a toggling clock signal (see Fig. 2-3, 6-8, 17, 20, 22-30, 36-40 and paragraph 0080-0093, 0109-0114, 0135-0140, 0168-0183, 0202).
Regarding claim 6, Miura et al. teach all claimed subject matter as applied in prior rejection of claim 4 on which this claim depends.
Miura et al. further teach, further comprising a buffer configured to delay the clock signal, wherein the command and address transition timings are aligned with the delayed clock signal (see Fig. 2-3, 6-8, 17, 20, 22-30, 36-40 and paragraph 0080-0093, 0109-0114, 0135-0140, 0168-0183, 0202-0204).
Regarding claim 7, Miura et al. teach all claimed subject matter as applied in prior rejection of claim 4 on which this claim depends.
Miura et al. further teach, wherein the transition timings include timings for a write sequence and/or a read sequence, and each timing is aligned with at least one of rising edges and falling edges of the clock signal (see Fig. 2-3, 6-8, 17, 20, 22-30, 36-40 and paragraph 0080-0093, 0109-0114, 0135-0140, 0168-0183).
Regarding claim 8, Miura et al. teach all claimed subject matter as applied in prior rejection of claim 7 on which this claim depends.
Miura et al. further teach, wherein the write sequence includes activation, write, and pre-charge, and the read sequence includes activation, read, and pre-charge (see Fig. 2-3, 6-8, 17, 20, 22-30, 36-40 and paragraph 0080-0093, 0109-0114, 0135-0140, 0168-0183, 0202-0203).
Regarding claim 9, Miura et al. teach all claimed subject matter as applied in prior rejection of claim 7 on which this claim depends.
Miura et al. further teach, further comprising a sequencer configured to provide a sequence command signal responsive to the clock signal, wherein the sequence command signal identifies the write sequence and/or the read sequence at predefined timings (see Fig. 2-3, 6-8, 17, 20, 22-30, 36-40 and paragraph 0080-0093, 0109-0114, 0135-0140, 0168-0180).
Regarding claim 10, Miura et al. teach all claimed subject matter as applied in prior rejection of claim 9 on which this claim depends.
Miura et al. further teach, further comprising a formatter configured to generate the command and address signal based on the sequence command signal in accordance with a predefined format (see Fig. 2-3, 6-8, 17, 20, 22-30, 36-40 and paragraph 0080-0093, 0109-0114, 0135-0140, 0168-0173).
Regarding claim 11, Miura et al. teach all claimed subject matter as applied in prior rejection of claim 10 on which this claim depends.
Miura et al. further teach, wherein the BTI controller includes the sequencer and the formatter as at least part of an algorithmic programmable circuit (see Fig. 2-3, 6-8, 17, 20, 22-30, 36-40 and paragraph 0080-0093, 0109-0114, 0135-0140, 0168-0183).
Regarding claim 12, Miura et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Miura et al. further teach, wherein the BTI controller is an NBTI controller (see Fig. 2-3, 6-8, 17, 20, 22-30, 36-40 and paragraph 0080-0093, 0109-0114, 0135-0140, 0168-0181).
Regarding independent claim 13, Miura et al. teach an apparatus, comprising: a memory device; and a bias temperature instability (BTI) controller configured to generate a command and address signal for memory testing (see Fig. 2-3, 6-8, 17, 20, 22-30, 36-40 and paragraph 0080-0093, 0109-0114, 0135-0140, 0168-0183, 0202-0204, 0255-0262 where memory device includes CTL_LOGIC controller where COM_GEN unit generate command and A_CONT unit generate address signal), wherein the command and address signal supplied to the memory device in an idle state causes a memory command and address latch circuit to output internal signals responsive to the received command and address signal to a memory bank logic circuit and a memory data latch circuit (see Fig. 2-3, 6-8, 17, 20, 22-30, 36-40 and paragraph 0080-0093, 0109-0114, 0135-0140, 0168-0183, 0202-0204, 0255-0262, see specially Fig.8 step 1-3 where idle state for read write testing).
Even though Miura et al. teach controller CTL_LOGIC unit including command and address generator, temperature measuring unit TMP but silent exclusively about a bias temperature instability (BTI) controller. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Miura et al. where temperature module of controller including command and address generator with idle state operation function as a bias temperature instability (BTI) controller in order to reduce data retention power and to improve speed and reliability of memory device (see paragraph 0221, 0223).
Regarding claim 14, Miura et al. teach all claimed subject matter as applied in prior rejection of claim 13 on which this claim depends.
Miura et al. further teach, further comprising an oscillator configured to generate a toggling clock signal, wherein the BTI controller generates the command and address signal having command and address transition timings aligned with at least one of a toggling clock signal and a delayed toggling clock signal responsive to the toggling clock signal (see Fig. 2-3, 6-8, 17, 20, 22-30, 36-40 and paragraph 0080-0093, 0109-0114, 0135-0140, 0168-0183, 0202).
Regarding claim 15, Miura et al. teach all claimed subject matter as applied in prior rejection of claim 14 on which this claim depends.
Miura et al. further teach, wherein the transition timings include timings for a memory testing operation including activation, write or read, and pre-charge, and each timing is aligned with at least one of rising edges and falling edges of the at least one of the toggling clock signal and the delayed toggling clock signal (see Fig. 2-3, 6-8, 17, 20, 22-30, 36-40 and paragraph 0080-0093, 0109-0114, 0135-0140, 0168-0183).
Regarding claim 16, Miura et al. teach all claimed subject matter as applied in prior rejection of claim 14 on which this claim depends.
Miura et al. further teach, wherein the BTI controller is an NBTI controller (see Fig. 2-3, 6-8, 17, 20, 22-30, 36-40 and paragraph 0080-0093, 0109-0114, 0135-0140, 0168-0173).
Regarding independent claim 17, Miura et al. teach a bias temperature instability (BTI) controller for a memory device, comprising: a sequencer configured to generate a sequence command signal responsive to a toggling clock signal (see Fig. 2-3, 6-8, 17, 20, 22-30, 36-40 and paragraph 0080-0093, 0109-0114, 0135-0140, 0168-0183, 0202-0204, 0255-0262 where INT generate sequence command for the operation responsive to CLK_GEN unit), wherein the sequence command signal identifies a memory test operation sequence at a first timing; and a formatter configured to generate a command and address signal based on the sequence command signal and the toggling clock signal in accordance with a format at a second timing (see Fig. 2-3, 6-8, 17, 20, 22-30, 36-40 and paragraph 0080-0093, 0109-0114, 0135-0140, 0168-0183, 0202-0204, 0255-0262 where memory device includes CTL_LOGIC controller where COM_GEN unit generate command and A_CONT unit generate address signal), wherein the command and address signal has command and address transition timings aligned with the toggling clock signal, and is decodable by a command and address control circuit of the memory device for command and address information (see Fig. 2-3, 6-8, 17, 20, 22-30, 36-40 and paragraph 0080-0093, 0109-0114, 0135-0140, 0168-0183, 0202-0204, 0255-0262).
Even though Miura et al. teach controller CTL_LOGIC unit including command and address generator, temperature measuring unit TMP but silent exclusively about a bias temperature instability (BTI) controller. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Miura et al. where temperature module of controller including command and address generator with idle state operation function as a bias temperature instability (BTI) controller in order to reduce data retention power and to improve speed and reliability of memory device (see paragraph 0221, 0223).
Regarding claim 18, Miura et al. teach all claimed subject matter as applied in prior rejection of claim 17 on which this claim depends.
Miura et al. further teach, wherein the command and address transition timings are further aligned with a delayed clock signal of the toggling clock signal in accordance with the format (see Fig. 2-3, 6-8, 17, 20, 22-30, 36-40 and paragraph 0080-0093, 0109-0114, 0135-0140, 0168-0183, 0202).
Regarding claim 19, Miura et al. teach all claimed subject matter as applied in prior rejection of claim 17 on which this claim depends.
Miura et al. further teach, wherein the transition timings include timings for transitioning a memory testing operation including activation, write or read, and pre-charge, and each timing is aligned with at least one of rising edges and falling edges of the at least one of the toggling clock signal (see Fig. 2-3, 6-8, 17, 20, 22-30, 36-40 and paragraph 0080-0093, 0109-0114, 0135-0140, 0168-0183, 0202-0204, 0255).
Regarding claim 20, Miura et al. teach all claimed subject matter as applied in prior rejection of claim 17 on which this claim depends.
Miura et al. further teach, wherein the BTI controller is an NBTI controller (see Fig. 2-3, 6-8, 17, 20, 22-30, 36-40 and paragraph 0080-0093, 0109-0114, 0135-0140, 0168).
Response to Arguments
Applicant's arguments filed 01/05/2026 have been fully considered but they are not persuasive.
Applicant argues (see page 8-10 of remarks) that Miura et al. do not disclose, "BTI controller". Examiner respectfully disagrees with this statement.
First, as per claim 1 and all other dependent claim, bias temperature instability (BTI) controller generates and output command and address signal for memory testing. So, any controller unit generates and output command and address signal for memory testing would be considered as BTI controller as the claim limitation did not specify any.
Second, The limitation “memory testing” would be interpreted broadly where any operation which are part of the memory testing like writing, reading operation like sending / receiving read / write command , address for reading /writing or any access operation also part of the memory testing operation as the claim did not specify any.
Second, the limitation “the command and address signal causes the memory device in the idle state to operate for the testing” clearly indicate that during idle state, memory device can operate for the testing ie. even receiving a command for testing during idle state or accessing the memory would be part of the memory testing operation during idle state. Again, as explained above, any kind of operation related to reading/writing the memory would be considered as testing.
In Fig.2 and paragraph 0173, 0179-0182, 0202, 0204, Miura et al. teach the controller unit CTL_LOGIC has command generator unit COM_GEN, FGEN and address generator unit A_CONT which generates and output command signal and address signal requires for DRAM testing i.e. reading / writing.
In Fig. 5-8, paragraph 0109-0114, Miura et al. further teach that “When the initialization ends, the memory module goes into the idle state T4 and prepares to accept accesses from external”, “the memory module waits for a command from external in the idle state”. This clearly indicate that idle state is part of the memory testing operation. So, claim 1 rejection is proper and maintained.
Regarding claim 13, applicant argues (see page 11 in remarks) that Miura fails to teach “the memory command address latch circuit that outputs internal signals responsive to the command and address signal generated by the BTI controller recited by claim 13”. Examiner respectfully disagrees with this statement.
In Fig. 17, 19 and paragraph 0135, 0138, 0219, Miura et al. teach command and address latch enable signal generated from the controller for DRAM memory bank (see Fig. 20) and “This pulse triggers a latching of these addresses and commands”. This clearly indicate that latch circuitry must be there in order to latch the command / address signal.
Applicant further argues in page 12, “Miura is silent with respect to the BTI controller that includes the claimed combination of a sequencer and a formatter in the manner recited by claim 17”. Examiner respectfully disagrees with this statement.
First, as per claim limitation “a sequencer configured to generate a sequence command signal responsive to a toggling clock signal” clearly indicate that any unit generate a sequence command signal responsive to a toggling clock signa would be called sequencer. Similarly, the limitation “a formatter configured to generate a command and address signal based on the sequence command signal and the toggling clock signal in accordance with a format at a second timing” would be interpreted broadly where “a format” can be any type of format as the claim limitation did not specify. So, any unit generate the command and address with any format based on the sequence command signal and the toggling clock signal would be called formatter. Also, the limitation “first timing” and “second timing” is broad as it did not specify.
In paragraph 0176, 0261, 0262, Miura et al. teach “The clock generator (CLK_GEN) generates a clock and supplies the clock to the DRAM and the control circuit (CTL_LOGIC)”, “The COM_GEN issues a command to the DRAM to be accessed synchronously with the clock generated by the CLK_GEN.”.
In Fig. 11-14, paragraph 0092, 0134, 0139, Miura et al. teach “data is read from the data register sequentially in units of 8 bits synchronously with the rising of the serial clock signal F-SC and is then output from the I/O signal lines I/00 to I/07” and ”data is already written sequentially from the DRAM address information held there”. This clearly indicate that data sequencer is there to sequentially write data or read from the memory with specific format of units of 8 bits by the formatter.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED A BASHAR whose telephone number is 469-295-9277 and fax number is (571)273-2908. The examiner can normally be reached on 9am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard T Elms can be reached on 5712721869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMED A BASHAR/Primary Examiner, Art Unit 2824