DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6/24/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 1 is objected to because of the following informalities: the claim appears to have a typographical error, "a transistor chi". For the purpose of examination, the examiner will interpret the above limitation as " a transistor chip".
Claim 7 is objected to because of the following informalities: the claim appears to have a typographical error, "said base sea". For the purpose of examination, the examiner will interpret the above limitation as " said base seat".
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, 6 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Otremba et al. US 2014/0084433 in view of Yamashita et al. US 2007/0069344.
Re claim 1, Otremba teaches a multi-chip package device (fig7) comprising:
a lead frame (401, fig7-9, [70]) made of a conducting material (metal, [20]), and having a base seat (401_1, fig7 and 9, [70]) that has an upper surface (top surface of 401_1, fig9, [75]) and a bottom surface (bottom surface of 401_1, fig9) opposite to said upper surface, and
a plurality of leads (leads around 401_1-3, fig7) that are spaced apart from each other, and that extend from said base seat (401_1, fig7 and 9, [70]);
a transistor chip (402_1, fig7 and 9, [72]) disposed on said upper surface of said base seat, and
including an active surface (top surface of 402_1, fig7 and 9, [72]), a rear surface (bottom surface of 402_1, fig7 and 9, [72]) that is opposite to said active surface.
Otremba does not explicitly a plurality of source electrode pads that are located on said active surface, a gate electrode that is located on said active surface.
Yamashita teaches a power semiconductor chip with a plurality of source electrode pads (8, fig3, [50]) that are located on said active surface (top surface of 3,fig3), a gate electrode (7, fig3, [17]) that is located on said active surface.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Otremba and Yamashita to form the gate pad and source pads as in fig3 of Yamashita. The motivation to do so is to prevent displacement of the contact leads and contain excessive rise in temperature (Yamashita, [50]).
Otremba in view of Yamashita teaches a drain electrode (Otremba, drain electrode on back of 402_1, fig9, [18, 72]; Yamashita, 9, fig3, [17]) that is located on said rear surface and that is electrically connected to said base seat (Otremba, 401_1, fig7 and 9, [70]);
a metallic frame (Otremba, 203, fig4 and 7, [56, 62]) having a main conducting part (Otremba, 225 in contact with source pads as in Yamshita, fig7 and 9, [63]) that covers said transistor chip (Otremba, 402_1 with gate and source pads arranged as in Yamashita fig3, fig7 and 9, [72]) and that is electrically connected to at least one of said source electrode pads (Yamashita, 8, fig3, [50]), and
a conducting leg (Otremba, 203_1, 203_2 and 203_3, fig9, [63]) integrally formed with said main conducting part (Otremba, 225, fig7 and 9, [63]), and extending from said main conducting part for externally electrical connection (Otremba, fig9), said conducting leg (Otremba, 203_1, 203_2 and 203_3, fig9, [63]) having a first conducting section (Otremba, 203_1 , fig4 and 9, [63]) that extends and bends from said main conducting part (Otremba, 225, fig7 and 9, [63]) and located at a height that is not lower than said main conducting part (Otremba, 203_1 formed above 225, fig7 and 9, [63]) and a second conducting section (Otremba, 203_2 and 203_3, fig7 and 9, [63]) that extends and bends from said first conducting section (Otremba, 203_1, fig4, 7 and 9, [63]) towards said lead frame (Otremba, 401, fig7-9, [70]), and that has a conducting bottom surface (Otremba, bottom surface of 203_3, fig7 and 9, [63]) being coplanar with said bottom surface of said base seat of said lead frame (Otremba, bottom surface of 401_1, fig9);
a circuit control chip (Otremba, 402_3, fig7, [71]) that is disposed on said upper surface of said base seat, that is electrically isolated from said base seat (Otremba, 401_1, fig7 and 9, [70]), and that is electrically connected to said transistor chip (Otremba, 402_1, fig7 and 9, [72]) and said leads (Otremba, leads around 401_1-3, fig7);
an encapsulation layer (Otremba, 404, fig8-9, [77]) enveloping said lead frame (Otremba, 401, fig7-9, [70]), said transistor chip (Otremba, 402_1, fig7 and 9, [72]), said main conducting part of said metallic frame (Otremba, 225, fig7 and 9, [63]), said first conducting section of said conducting leg of said metallic frame (Otremba, 203_1 , fig9, [63]), and said circuit control chip (Otremba, 402_3, fig7, [71]) and exposing said bottom surface of said base seat (Otremba, bottom surface of 401_1, fig9) and said second conducting section of said conducting leg (Otremba, 203_3, fig7 and 9, [63]).
Re claim 3, Otremba in view of Yamashita teaches the multi-chip package device as claimed in claim 1, wherein: said transistor chip includes four of said source electrode pads (Yamashita, 8, fig3, [50]), said main conducting part being electrically connected to two of said source electrode pads (Yamashita, 6 connected with all four source pads, fig4, [18]); and a gap (Yamashita, gap between 8 in X direction, fig3, [50]) is formed between said two of said source electrode pads.
Re claim 6, Otremba in view of Yamashita teaches the multi-chip package device as claimed in claim 1, wherein at least one of said source electrode pads and said gate electrode are electrically connected to said circuit control chip via bonding wires (Otremba, 403_1 controls gate of 402_1, fig7, [72]).
Re claim 10, Otremba in view of Yamashita teaches the multi-chip package device as claimed in claim 1, wherein said main conducting part covers at least 50% of a surface area of said active surface of said transistor chip (225 of Otremba in contact with 8 of Yamashita of about 80% of top surface of chip).
Claim(s) 5 is rejected under 35 U.S.C. 103 as being unpatentable over Otremba et al. US 2014/0084433 in view of Yamashita et al. US 2007/0069344 and Tsuchida et al. US 2004/0026770.
Re claim 5, Otremba in view of Yamashita teaches the multi-chip package device as claimed in claim 1, wherein: said first conducting section (Otremba, 203_1 , fig9, [63]) has an extending portion (Otremba, part of 203_1 with slope around 225 , fig9, [63]) that extends from said main conducting part (Otremba, 225, fig7 and 9, [63]), and that extends at a height not lower than said main conducting part (Otremba, top surface of sloped part of 203_1 around 225 located above top surface of 225 , fig9, [63]), and a parallel portion (Otremba, 203_1 with top surface parallel to 401b around 225 , fig9, [63]) that is connected to said extending portion (Otremba, part of 203_1 with slope around 225 , fig9, [63]) and that is parallel to said main conducting part (Otremba, 225, fig7 and 9, [63]); said second conducting section (Otremba, 203_2 and 203_3, fig7 and 9, [63]) has an inclined conducting portion (Otremba, 203_2, fig7 and 9, [63]) that is connected to said parallel portion of said first conducting section.
Otremba does not explicitly show bent at an angle ranging from 60o to 80o relative to said parallel portion; and a planar conducting portion that is connected to said inclined conducting portion, that is bent at an angle ranging from 60o to 80o relative to said inclined conducting portion, and that has said conducting bottom surface.
Tsushida teaches adjusting bend angles to achieve desirable distance of lead from the chip (fig1B).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Otremba, Yamashita and Tsushida to adjust the bending angle of 203_2. The motivation to do so is to achieve desired distance for 203_3 according to the location of the chip and size of the lead frame with separation distance for safe operation (Tsushida, [30, 35]).
Allowable Subject Matter
Claim 2, 4, 7-9 and 11-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim.
Specifically, the limitations are material to the inventive concept of the application in hand to reduce stress buildup from the leads and reduce damage at interface between encapsulation and conducing legs.
Conclusion
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/XIAOMING LIU/Examiner, Art Unit 2812
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