Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on October 21, 2024 and August 11, 2025 were in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claims 1-3, 5-13 and 15-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-23 of U.S. Patent No. US 10,319,854 B1. Although the claims at issue are not identical, they are not patentably distinct from each other.
Regarding Claim 1, Patent No.: US 10,319,854 B1 discloses at least one integrated circuit high voltage switching device, including: (a) a transistor structure including a source, a gate, an internal drain, and a channel between the source and internal drain (claim 1); (b) a modulated resistance region co-fabricated with the transistor structure and electrically connected to the internal drain of the transistor structure (claim 1); (c) a drain electrically connected to the modulated resistance region and configured to be coupled to a voltage source (claim 1); and (d) at least one voltage-drop modulation gate, fabricated between the internal drain and the drain in a non-overlapping relationship to the drain and in relation to the modulated resistance region so as to control the resistance of the modulated resistance region in response to an applied first bias voltage or second bias voltage (claim 1); wherein (1) when the first bias voltage is applied to the at least one voltage-drop modulation gate and the FET transistor structure is switched ON, the modulated resistance region provides a low-resistance conduction path between the source and the drain, and (2) when the second bias voltage is applied to the at least one voltage-drop modulation gate, the modulated resistance region is depleted sufficiently to provide a high-resistance conduction path between the drain and the internal drain, the high-resistance conduction path being sufficient to drop an applied voltage on the drain to less than a breakdown voltage BVDSS of the FET transistor structure (claim 1).
Regarding Claim 2, Patent No.: US 10,319,854 B1, as applied to claim 1, discloses the at least one integrated circuit high voltage switching device, wherein the breakdown voltage of the at least one voltage-drop modulation gate is greater than the breakdown voltage of the transistor structure (claim 11).
Regarding Claim 3, Patent No.: US 10,319,854 B1, as applied to claim 1, discloses the at least one integrated circuit high voltage switching device, further including a plurality of voltage-drop modulation gates series-connected between the internal drain and the drain (claim 2).
Regarding Claim 5, Patent No.: US 10,319,854 B1, as applied to claim 1, discloses the at least one integrated circuit high voltage switching device, further including a silicide layer formed on surface regions of the modulated resistance region adjacent the at least one voltage-drop modulation gate (claim 14).
Regarding Claim 6, Patent No.: US 10,319,854 B1, as applied to claim 1, discloses the at least one integrated circuit high voltage switching device, wherein the integrated circuit high voltage switching device is fabricated on a silicon-on-insulator substrate using a CMOS process (claim 9).
Regarding Claim 7, Patent No.: US 10,319,854 B1, as applied to claim 1, discloses the at least one integrated circuit high voltage switching device, wherein when the second bias voltage is sufficiently negative with respect to a threshold voltage for the modulated resistance region, the modulated resistance region is essentially fully depleted and substantially pinches off current flow through the modulated resistance region (claim 15).
Regarding Claim 8, Patent No.: US 10,319,854 B1, as applied to claim 1, discloses the at least one integrated circuit high voltage switching device, wherein the at least one voltage-drop modulation gate is fabricated over a portion of the modulated resistance region, and surface regions of the modulated resistance region adjacent to the at least one voltage-drop modulation gate are doped with a material having a selected polarity and at a higher doping concentration than the portion of the modulated resistance region under the at least one voltage-drop modulation gate (claim 13).
Regarding Claim 9, Patent No.: US 10,319,854 B1, as applied to claim 1, discloses the at least one integrated circuit high voltage switching device, wherein the modulated resistance region and the source and the drain comprise semiconductor regions of a selected polarity, doped to at least about 2 orders of magnitude less than the source and drain (claim 22).
Regarding Claim 10, Patent No.: US 10,319,854 B1 discloses at least one integrated circuit high voltage switching device fabricated on a silicon-on-insulator substrate, including: (a) a transistor structure including a source, a gate, an internal drain, and a channel between the source and internal drain (claims 1 & 19); (b) a modulated resistance region co-fabricated with the transistor structure and electrically connected to the internal drain of the transistor structure (claims 1 & 19); (c) a drain electrically connected to the modulated resistance region and configured to be coupled to a voltage source (claims 1 & 19); and (d) at least one voltage-drop modulation gate, fabricated between the internal drain and the drain in a non-overlapping relationship to the drain and in relation to the modulated resistance region so as to control the resistance of the modulated resistance region in response to an applied first bias voltage (claims 1 & 19); (e) a deep well region proximate to at least a portion of the modulated resistance region (claim 19); and (f) at least one electrical contact coupled to the deep well region for applying a second bias voltage to the deep well region (claim 19).
Regarding Claim 11, Patent No.: US 10,319,854 B1, as applied to claim 10, discloses the at least one integrated circuit high voltage switching device, wherein the at least one electrical contact is a substrate contact (claim 21).
Regarding Claim 12, Patent No.: US 10,319,854 B1, as applied to claim 10, discloses the at least one integrated circuit high voltage switching device, wherein the breakdown voltage per voltage-drop modulation gate is greater than the breakdown voltage of the transistor structure (claim 11).
Regarding Claim 13, Patent No.: US 10,319,854 B1, as applied to claim 10, discloses the at least one integrated circuit high voltage switching device, further including a plurality of voltage-drop modulation gates series-connected between the internal drain and the drain (claim 2).
Regarding Claim 15, Patent No.: US 10,319,854 B1, as applied to claim 10, discloses the at least one integrated circuit high voltage switching device, further including a silicide layer formed on surface regions of the modulated resistance region adjacent the at least one voltage-drop modulation gate (claim 14).
Regarding Claim 16, Patent No.: US 10,319,854 B1, as applied to claim 10, discloses the at least one integrated circuit high voltage switching device, wherein the integrated circuit high voltage switching device is fabricated on a silicon-on-insulator substrate using a CMOS process (claim 12).
Regarding Claim 17, Patent No.: US 10,319,854 B1, as applied to claim 10, discloses the at least one integrated circuit high voltage switching device, wherein when the first bias voltage is sufficiently negative with respect to a threshold voltage for the modulated resistance region, the modulated resistance region is essentially fully depleted and substantially pinches off current flow through the modulated resistance region (claim 15).
Regarding Claim 18, Patent No.: US 10,319,854 B1, as applied to claim 10, discloses the at least one integrated circuit high voltage switching device, wherein the deep well region has the same polarity as the modulated resistance region (claim 20).
Regarding Claim 19, Patent No.: US 10,319,854 B1, as applied to claim 10, discloses the at least one integrated circuit high voltage switching device, wherein the at least one voltage-drop modulation gate controls the resistance of the modulated resistance region by at least partially depleting at least a portion of the modulated resistance region upon application of the first bias voltage to the at least one voltage-drop modulation gate, and wherein the deep well region further depletes at least a portion of the modulated resistance region upon application of the second bias voltage to the at least one substrate contact (claim 21).
Regarding Claim 20, Patent No.: US 10,319,854 B1, as applied to claim 10, discloses the at least one integrated circuit high voltage switching device, wherein the at least one voltage-drop modulation gate is fabricated over a portion of the modulated resistance region, and surface regions of the modulated resistance region adjacent to the at least one voltage-drop modulation gate are doped with a material having a selected polarity and at a higher doping concentration than the portion of the modulated resistance region under the at least one voltage-drop modulation gat (claim 13).
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-21 of U.S. Patent No. US 10,923,592 B2. Although the claims at issue are not identical, they are not patentably distinct from each other.
Regarding Claim 1, Patent No.: US 10,923,592 B2 discloses at least one integrated circuit high voltage switching device, including: (a) a transistor structure including a source, a gate, an internal drain, and a channel between the source and internal drain (claim 1); (b) a modulated resistance region co-fabricated with the transistor structure and electrically connected to the internal drain of the transistor structure (claim 1); (c) a drain electrically connected to the modulated resistance region and configured to be coupled to a voltage source (claim 1); and (d) at least one voltage-drop modulation gate, fabricated between the internal drain and the drain in a non-overlapping relationship to the drain and in relation to the modulated resistance region so as to control the resistance of the modulated resistance region in response to an applied first bias voltage or second bias voltage (claim 1); wherein (1) when the first bias voltage is applied to the at least one voltage-drop modulation gate and the FET transistor structure is switched ON, the modulated resistance region provides a low-resistance conduction path between the source and the drain, and (2) when the second bias voltage is applied to the at least one voltage-drop modulation gate, the modulated resistance region is depleted sufficiently to provide a high-resistance conduction path between the drain and the internal drain, the high-resistance conduction path being sufficient to drop an applied voltage on the drain to less than a breakdown voltage BVDSS of the FET transistor structure (claim 1).
Regarding Claim 2, Patent No.: US 10,923,592 B2, as applied to claim 1, discloses the at least one integrated circuit high voltage switching device, wherein the breakdown voltage of the at least one voltage-drop modulation gate is greater than the breakdown voltage of the transistor structure (claim 2).
Regarding Claim 3, Patent No.: US 10,923,592 B2, as applied to claim 1, discloses the at least one integrated circuit high voltage switching device, further including a plurality of voltage-drop modulation gates series-connected between the internal drain and the drain (claim 3).
Regarding Claim 4, Patent No.: US 10,923,592 B2, as applied to claim 3, discloses the at least one integrated circuit high voltage switching device, wherein the plurality of voltage-drop modulation gates are configured to be biased in a step-wise fashion to achieve a total voltage drop of less than the breakdown voltage BVDSS of the FET transistor structure without imposing an input voltage on any one voltage-drop modulation gate that exceeds the breakdown voltage BVDSS for such voltage-drop modulation gate (claim 11).
Regarding Claim 5, Patent No.: US 10,923,592 B2, as applied to claim 1, discloses the at least one integrated circuit high voltage switching device, further including a silicide layer formed on surface regions of the modulated resistance region adjacent the at least one voltage-drop modulation gate (claim 4).
Regarding Claim 6, Patent No.: US 10,923,592 B2, as applied to claim 1, discloses the at least one integrated circuit high voltage switching device, wherein the integrated circuit high voltage switching device is fabricated on a silicon-on-insulator substrate using a CMOS process (claim 5).
Regarding Claim 7, Patent No.: US 10,923,592 B2, as applied to claim 1, discloses the at least one integrated circuit high voltage switching device, wherein when the second bias voltage is sufficiently negative with respect to a threshold voltage for the modulated resistance region, the modulated resistance region is essentially fully depleted and substantially pinches off current flow through the modulated resistance region (claim 6).
Regarding Claim 8, Patent No.: US 10,923,592 B2, as applied to claim 1, discloses the at least one integrated circuit high voltage switching device, wherein the at least one voltage-drop modulation gate is fabricated over a portion of the modulated resistance region, and surface regions of the modulated resistance region adjacent to the at least one voltage-drop modulation gate are doped with a material having a selected polarity and at a higher doping concentration than the portion of the modulated resistance region under the at least one voltage-drop modulation gate (claim 17).
Regarding Claim 9, Patent No.: US 10,923,592 B2, as applied to claim 1, discloses the at least one integrated circuit high voltage switching device, wherein the modulated resistance region and the source and the drain comprise semiconductor regions of a selected polarity, doped to at least about 2 orders of magnitude less than the source and drain (claim 15).
Regarding Claim 10, Patent No.: US 10,923,592 B2 discloses at least one integrated circuit high voltage switching device fabricated on a silicon-on-insulator substrate, including: (a) a transistor structure including a source, a gate, an internal drain, and a channel between the source and internal drain (claims 1 & 18); (b) a modulated resistance region co-fabricated with the transistor structure and electrically connected to the internal drain of the transistor structure (claims 1 & 18); (c) a drain electrically connected to the modulated resistance region and configured to be coupled to a voltage source (claims 1 & 18); and (d) at least one voltage-drop modulation gate, fabricated between the internal drain and the drain in a non-overlapping relationship to the drain and in relation to the modulated resistance region so as to control the resistance of the modulated resistance region in response to an applied first bias voltage (claims 1 & 18); (e) a deep well region proximate to at least a portion of the modulated resistance region (claims 18-19); and (f) at least one electrical contact coupled to the deep well region for applying a second bias voltage to the deep well region (claims 18-19).
Regarding Claim 11, Patent No.: US 10,923,592 B2, as applied to claim 10, discloses the at least one integrated circuit high voltage switching device, wherein the at least one electrical contact is a substrate contact (claim 20).
Regarding Claim 12, Patent No.: US 10,923,592 B2, as applied to claim 10, discloses the at least one integrated circuit high voltage switching device, wherein the breakdown voltage per voltage-drop modulation gate is greater than the breakdown voltage of the transistor structure (claim 9).
Regarding Claim 13, Patent No.: US 10,923,592 B2, as applied to claim 10, discloses the at least one integrated circuit high voltage switching device, further including a plurality of voltage-drop modulation gates series-connected between the internal drain and the drain (claim 10).
Regarding Claim 14, Patent No.: US 10,923,592 B2, as applied to claim 13, discloses the at least one integrated circuit high voltage switching device, wherein the plurality of voltage-drop modulation gates are configured to be biased in a step-wise fashion to achieve a total voltage drop of less than the breakdown voltage BVDSS of the FET transistor structure without imposing an input voltage on any one voltage-drop modulation gate that exceeds the breakdown voltage BVDSS for such voltage-drop modulation gate (claim 11).
Regarding Claim 15, Patent No.: US 10,923,592 B2, as applied to claim 10, discloses the at least one integrated circuit high voltage switching device, further including a silicide layer formed on surface regions of the modulated resistance region adjacent the at least one voltage-drop modulation gate (claim 12).
Regarding Claim 16, Patent No.: US 10,923,592 B2, as applied to claim 10, discloses the at least one integrated circuit high voltage switching device, wherein the integrated circuit high voltage switching device is fabricated on a silicon-on-insulator substrate using a CMOS process (claim 13).
Regarding Claim 17, Patent No.: US 10,923,592 B2, as applied to claim 10, discloses the at least one integrated circuit high voltage switching device, wherein when the first bias voltage is sufficiently negative with respect to a threshold voltage for the modulated resistance region, the modulated resistance region is essentially fully depleted and substantially pinches off current flow through the modulated resistance region (claims 6 & 8).
Regarding Claim 18, Patent No.: US 10,923,592 B2, as applied to claim 10, discloses the at least one integrated circuit high voltage switching device, wherein the deep well region has the same polarity as the modulated resistance region (claim 21).
Regarding Claim 19, Patent No.: US 10,923,592 B2, as applied to claim 10, discloses the at least one integrated circuit high voltage switching device, wherein the at least one voltage-drop modulation gate controls the resistance of the modulated resistance region by at least partially depleting at least a portion of the modulated resistance region upon application of the first bias voltage to the at least one voltage-drop modulation gate, and wherein the deep well region further depletes at least a portion of the modulated resistance region upon application of the second bias voltage to the at least one substrate contact (claim 19).
Regarding Claim 20, Patent No.: US 10,923,592 B2, as applied to claim 10, discloses the at least one integrated circuit high voltage switching device, wherein the at least one voltage-drop modulation gate is fabricated over a portion of the modulated resistance region, and surface regions of the modulated resistance region adjacent to the at least one voltage-drop modulation gate are doped with a material having a selected polarity and at a higher doping concentration than the portion of the modulated resistance region under the at least one voltage-drop modulation gat (claim 17).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Zuniga et al. (Patent No.: US 7,405,443 B1) substantially discloses at least one integrated circuit high voltage switching device, including: (a) a transistor structure including a source, a gate, an internal drain, and a channel between the source and internal drain (Column 5, Lines 38-61 – also see Fig. 3A – FET with source 306, gate 310, the space between the two gates 314 & 318 can be considered to constitute the internal drain); (b) a modulated resistance region co-fabricated with the transistor structure and electrically connected to the internal drain of the transistor structure (Column 3, Lines 44-58, Column 5, Lines 49-55, also Column 7, Lines 1-14 – also see Figs. 3A & 5 – voltage drop modulation gate 312, modulated resistance region is located underneath the modulation gate); (c) at least one voltage-drop modulation gate, fabricated with respect to the modulated resistance region so as to control the resistance of the modulated resistance region (Column 3, Lines 44-58, Column 5, Lines 49-55, also Column 7, Lines 1-14 – also see Figs. 3A & 5 – voltage drop modulation gate 312); and (d) a drain electrically connected to the modulated resistance region and configured to be coupled to a voltage source (Column 5, Lines 38-61 – also see Fig. 3A – drain 304).
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08/20/2026
/SYED I GHEYAS/Primary Examiner, Art Unit 2893
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