DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/24/2024 has been considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4,7,10,16,17,19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Briere (US 2007/0026587).
Regarding claim 1, Briere teaches a semiconductor device in fig. 2 comprising:
a two-dimensional (2D) material layer (14) extending in a first direction (refer to horizontal or x-axis direction);
a source electrode and a drain electrode (16/18) each electrically connected to the 2D material layer (14);
an insulating layer (22/24) on the 2D material layer (14); and
a gate electrode (26) being apart from the 2D material layer in a second direction (refer to vertical or y-axis direction) perpendicular to the first direction,
wherein the insulating layer includes a dopant (see par. 29).
Regarding claim 4, Briere teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, Brier teaches the insulating layer comprises traps (see par. 28).
Regarding claim 7, Briere teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, Brier teaches a region of the 2D material layer overlapping the gate electrode in the second direction exhibits semiconductor characteristics (see pars. 26-27).
Regarding claim 10, Briere teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, Brier teaches the dopant is uniformly present in an entire region of the insulating layer (see par. 29).
Regarding claim 16, Briere teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, Brier teaches the semiconductor device is a field effect transistor (see fig. 2).
Regarding claim 17, Briere teaches a method of manufacturing a semiconductor device in fig. 2, the method comprising:
forming a two-dimensional (2D) material layer (14) extending in a first direction (refer to horizontal or x-axis direction) on a substrate (10);
forming a source electrode and a drain electrode (16/18) on edges of the substrate;
forming an insulating layer (22/24) on the 2D material layer (refer to 14); and
implanting a dopant into the insulating layer (see par. 29).
Regarding claim 19, Briere teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, Briere teaches after the implanting, forming a gate electrode on the insulating layer (see par. 29).
Regarding claim 20, Briere teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, Briere teaches after the implanting, annealing the insulating layer (see par. 29).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 6, 9 and 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over Briere (US 2007/0026587) as applied to claim 1 above, and further in view of Oh (US 2016/0104790).
Regarding claim 6, Briere teaches all the limitations of the claimed invention for the same reasons as set forth above except for a region of the 2D material layer overlapping the gate electrode in the second direction operates as a channel.
Oh teaches the same field of an endeavor wherein a region of the 2D material layer overlapping the gate electrode in the second direction operates as a channel (see par. 39 and fig. 3).
Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include a region of the 2D material layer overlapping the gate electrode in the second direction operates as a channel as taught by Oh in the teaching of Briere in order to obtain a high mobility, and the band gap characteristic may be readily controlled by a doping material (see par. 31).
Regarding claim 9, Briere teaches all the limitations of the claimed invention for the same reasons as set forth above except for the 2D material layer comprises graphene, transition metal dichalcogenide (TMD), or black phosphorus.
Oh teaches the same field of an endeavor wherein the 2D material layer comprises graphene, transition metal dichalcogenide (TMD), or black phosphorus (see par. 31).
Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include the 2D material layer comprises graphene, transition metal dichalcogenide (TMD), or black phosphorus as taught by Oh in the teaching of Briere in order to obtain a high mobility, and the band gap characteristic may be readily controlled by a doping material (see par. 31).
Regarding claim 11, Briere teaches all the limitations of the claimed invention for the same reasons as set forth above except for the insulating layer comprises metal oxide.
Oh teaches the same field of an endeavor wherein the insulating layer comprises metal oxide (see par. 35).
Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include the insulating layer comprises metal oxide as taught by Oh in the teaching of Briere because it reduces tunneling leakage.
Regarding claim 12, Briere and Oh teach all the limitations of the claimed invention for the same reasons as set forth above. Besides, Oh teaches the metal oxide comprises Si, Al, La, Ti, Zr, Hf, Mg, Ge, Y, Lu, or Sr (see par. 35).
Regarding claim 13, Briere teaches all the limitations of the claimed invention for the same reasons as set forth above except for the 2D material layer comprises a plurality of layers.
Oh teaches the same field of an endeavor wherein the 2D material layer comprises a plurality of layers (see par. 31).
Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include the 2D material layer comprises a plurality of layers as taught by Oh in the teaching of Briere in order to obtain a high mobility, and the band gap characteristic may be readily controlled by a doping material (see par. 31).
Regarding claim 14, Briere teaches all the limitations of the claimed invention for the same reasons as set forth above except for the gate electrode comprises metal, conductive nitride, or conductive oxide.
Oh teaches the same field of an endeavor wherein the gate electrode comprises metal, conductive nitride, or conductive oxide (see par. 36).
Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include the gate electrode comprises metal, conductive nitride, or conductive oxide as taught by Oh in the teaching of Briere since metal, conductive nitride or conductive oxide are commonly used in the HEMT device because they have relatively high melting points and good thermal/chemical stability.
Claims 15 is rejected under 35 U.S.C. 103 as being unpatentable over Briere (US 2007/0026587) as applied to claim 1 above, and further in view of Dang (US 2008/0111157).
Regarding claim 15, Briere teaches all the limitations of the claimed invention for the same reasons as set forth above except for a width of the gate electrode is about 10 nm to about 100 nm.
Dang teaches the same field of an endeavor wherein a width of the gate electrode is about 10 nm to about 100 nm (see par. 43).
Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include a width of the gate electrode is about 10 nm to about 100 nm as taught by Dang in the teaching of Briere so that the gate electrode has a gate capacitance sufficiently low enough to permit use in a semiconductor device for sub-millimeter wave amplifier operating from 300 GHz to 3 THz (see par. 43).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Briere (US 2007/0026587) as applied to claim 1 above, and further in view of Takao (JP 2504442 B2)
Regarding claim 18, Briere teaches all the limitations of the claimed invention for the same reasons as set forth above except for before the implanting, forming a gate electrode on the insulating layer, wherein the implanting implants the dopant into the insulating layer by using the gate electrode as a mask.
Takao teaches the same field of an endeavor wherein before the implanting, forming a gate electrode (76) to serves as a doping mask (see fig. 7a and its corresponding text).
Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include before the implanting, forming a gate electrode to serves as a doping mask as taught by Takao in the teaching of Briere such that the implanting implants the dopant into the insulating layer by using the gate electrode as a mask because it simplifies the manufacturing step of making the device.
Allowable Subject Matter
Claim 2 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest “the dopant is present in both edge regions of the insulating layer that do not overlap the gate electrode in the second direction.”
Claim 3 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest “the dopant comprises P+, As+, B-, Al-, or H+.”
Claim 5 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest “the traps are present in both edge regions of the insulating layer that do not overlap the gate electrode in the second direction.”
Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest “an edge region of the 2D material layer that does not overlap the gate electrode in the second direction exhibits metal characteristics.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Niki Tram Nguyen whose telephone number is (571) 272-5526. The examiner can normally be reached on 6:00am-4:00pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Steven Loke can be reached on (703)872-9306. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NIKI H NGUYEN/ Primary Examiner, Art Unit 2818
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