Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on June 24, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Amendment
The Amendment filed June 4, 2026 has been entered. Claims 1-20 remain pending in the application. Claims 1-2, 6-11, & 14-17 have been amended.
Response to Arguments
Applicant's arguments filed June 4, 2026, please refer to pp. 9-13 of Applicant remarks, have been fully entered and considered. In light of the amendments, the rejection(s) have been withdrawn. However, upon further consideration, and in light of the amendments, new ground(s) of rejection(s) have been made.
The Applicant has further presented a set of arguments, pointing out their rationale of how the prior art reference(s) made of record in the most recent Non-Final Office Action, mailed March 5, 2026, do not reach, suggest, and/or disclose the currently amended independent claim 1, and similarly amended independent claims 8 & 15 limitations, “each electronic switch in the set of electronic switches comprises a respective control node to receive a stress test voltage,” “coupling a first end of each coupling channel of a set of coupling channels to a common test node and a second end of each coupling channel of the set of coupling channels to the respective control node of a respective one of the electronic switches in the set of electronic switches, wherein the set of coupling channels is configured to propagate application of the stress test voltage from the common test node to the respective control node of the electronic switches in the set of electronic switches,” “based on a calibration enable signal having a first logic value, coupling a first input node of each comparator circuit of a set of comparator circuits to the respective control node of the respective one of the electronic switches in the set of electronic switches,” and “sensing, at the first input nodes of the set of comparator circuits, a set of control voltages comprising each control voltage sensed at the respective control node of the respective one of the electronic switches in the set of electronic switches.” To further encompass additional amendments, please see the attached amended claim 1 limitations presented in the amended claims received June 4, 2026.
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Applicant’s arguments have been fully considered but they are not persuasive. In light of the amendment(s), a new ground(s) of rejection(s) have been made in view of Pan et al. (US2017/0059645A1).
Applicant in their submitted response, see pp. 9-10 of Applicant remarks, presents the first argument that the prior art reference(s) Jang (US2008/0295605), in view of Zeng (US2015/0381148), and further in view of Neidorff (US2020/0200815), as cited by the Applicant, do not teach, suggest, and/or disclose individually or in combination, “each electronic switch in the set of electronic switches comprises a respective control node to receive a stress test voltage,” of amended independent claim 1 and similarly amended independent claims 8 & 15.
The Examiner respectfully disagrees and would like break the argument presented into two parts. The first part the Examiner would like to highlight is how prior art references Jang (US2008/0295605), in view of Zeng (US2015/0381148), in view of Neidorff (US2020/0200815), in light of the amendments, further in view of Pan (US2017/0059645A1), read on “each electronic switch in the set of electronic switches comprises a respective control node to receive a stress test voltage,” which was previously presented in the Non-Final OA (pp.3-9) prior to amendments. The Applicant mentions that “a bit signal ADDi applied to the gates of TR1 and TR3 and a high voltage VPP applied to the gate of the transistor TR2” on pg. 10, no additional evidence or rational is provided in regard to why the primary reference does not teach the claim language limitations. The first part the Examiner would like to highlight is there is insufficient explanation of rationale. The remarks do not provide any specific reasons, but rather generalizations not tied to the facts of the application, as to why either the findings of fact or the legal conclusion of obviousness in the rejection is allegedly in error. Please refer to MPEP 2143(I), 2143.02(I), and 2143.02(II). Further, a combination rejection cannot be overcome by arguing that the primary reference alone fails to teach a specific limitation. The proper test is whether the combined teachings of the prior art would have suggested the claimed invention to a POSITA. Please refer to MPEP 2145(IV). Applicant’s reply fails to address the combined teaching of the applied references and instead argues that the primary reference individually does not teach all of the claim limitations. The second part the Examiner would like to highlight is the additional prior art references, Pan et al. (US2017/0059645A1), in light of the amendments in claim 1, and Zeng (US2015/0381148), further read on the claim language limitation(s). Pan teaches an addressable test circuit where the gate (G) end of each transistor under test (DUT) is connected to a common test signal line (GF) through respective switches (SGF), and states that the common (GF) signal line is used to “force corresponding voltage to G end,” in Fig. 9D; [0024] & [0082]-[0084]. Zeng teaches utilizing a dedicated stress voltage generator to apply a “stress voltage” directly to a gate terminal during a testing mode, Fig. 1B; [0017]. A POSITA would have found it obvious to modify the function block of Jang with the centralized addressing and testing architecture of Pan, utilizing the stress voltage generator of Zeng. In the combined, modified circuit, the control nodes (gates) of the electronic switches (TR1-TR3) would be coupled to a common test node (GF) to receive a uniform stress test voltage during the test mode.
Applicant in their submitted response, see pp. 9-10 of Applicant remarks, presents the second argument that the art reference(s) Jang (US2008/0295605), in view of Zeng (US2015/0381148), and further in view of Neidorff (US2020/0200815), as cited by the Applicant, do not teach, suggest, and/or disclose individually or in combination, “based on a calibration enable signal having a first logic value, coupling a first input node of each comparator circuit of a set of comparator circuits to the respective control node of the respective one of the electronic switches in the set of electronic switches,” and that “Each of the gates of transistors TR1, TR2, TR3 (i.e., the respective control node of the respective one of the electronic switches) of the function block 200 are never coupled to the first input nodes N11/N12 and N21/N22 of each comparator 411/421” of amended independent claim 1 and similarly amended independent claims 8 & 15.
The Examiner respectfully disagrees and would like break the argument presented into two parts. The first part the Examiner would like to highlight is how prior art references Jang (US2008/0295605), in view of Zeng (US2015/0381148), in view of Neidorff (US2020/0200815), and in light of the amendments, further in view of Pan (US2017/0059645A1), read on “based on a calibration enable signal having a first logic value, coupling a first input node of each comparator circuit of a set of comparator circuits to the respective control node of the respective one of the electronic switches in the set of electronic switches,” which was previously presented in the Non-Final OA (pp.3-9) prior to amendments. The Applicant mentions that Figs. 1 & 5 of Jang show “detection signal generation circuit 400” receiving inputs from the “drain-side output nodes” Spp and Snn, rather than directly from “the transistors TR1-TR3.” The Examiner appreciates the explanation and additional evidence; however it is noted that a combination rejection cannot be overcome by arguing that the primary reference alone fails to teach a specific limitation. The proper test is whether the combined teachings of the prior art would have suggested the claimed invention to a POSITA. Please refer to MPEP 2145(IV). Applicant’s reply fails to address the combined teaching of the applied references and instead argues that the primary reference individually does not teach all of the claim limitations. The second part the Examiner would like to highlight is new prior art reference, Pan et al. (US2017/0059645A1), in light of the amendments in claim 1, further reads on the claim language limitation(s). Pan teaches the necessity of sensing electrical parameters at the gate terminal “G end” of the transmission under test, setting a dedicated sense voltage signal line, GL, that connects directly to the control node “G end,” stating that “GL sense voltage signal line, it senses the voltage of G end to adjust the voltage drop pass by switch,” and further teaches that coupling to the GL sense line is executed via switches (e.g., SGL) that are selectively activated based on selection/enable signals generated during the test mode, addressable test circuit where the gate (G) end in [0099]-[0100]. A POSITA would have found it obvious to modify the sensing architecture of Jang with the gate-sensing topology of Pan. In the combined circuit, the calibration enable signal (test mode signal) would actuate the switches (SGL) to couple the first input node of Jang’s comparator circuits directly to the respective control node (gate) of the electronic switches via the GL sense line.
Applicant in their submitted response, see pp. 10-11 of Applicant remarks, presents the third argument that the art reference(s) Jang (US2008/0295605), in view of Zeng (US2015/0381148), and further in view of Neidorff (US2020/0200815), as cited by the Applicant, do not teach, suggest, and/or disclose individually or in combination, “coupling a first end of each coupling channel of a set of coupling channels to a common test node and a second end of each coupling channel of the set of coupling channels to the respective control node of a respective one of the electronic switches in the set of electronic switches,” of amended independent claim 1 and similarly amended independent claims 8 & 15.
The Examiner respectfully disagrees and would like break the argument presented into two parts. The first part the Examiner would like to highlight is how prior art references Jang (US2008/0295605), in view of Zeng (US2015/0381148), in view of Neidorff (US2020/0200815), and in light of the amendments, further in view of Pan (US2017/0059645A1), read on “coupling a first end of each coupling channel of a set of coupling channels to a common test node and a second end of each coupling channel of the set of coupling channels to the respective control node of a respective one of the electronic switches in the set of electronic switches,” which was previously presented in the Non-Final OA (pp.3-9) prior to amendments. The Applicant mentions that prior art reference Zeng illustrates the “variable reference voltage (VarREF)” coupled to the ”gate terminal transistor 112.” The Examiner appreciates the explanation and additional evidence; however it is noted that a combination rejection cannot be overcome by arguing that the secondary reference (Zeng) alone fails to teach a specific limitation. The proper test is whether the combined teachings of the prior art would have suggested the claimed invention to a POSITA. Please refer to MPEP 2145(IV). Applicant’s reply fails to address the combined teaching of the applied references and instead argues that the secondary reference individually does not teach all of the claim limitations. The second part the Examiner would like to highlight is new prior art reference, Pan et al. (US2017/0059645A1), in light of the amendments in claim 1, further reads on the claim language limitation(s). Pan teaches an addressable test circuit applied to a plurality of transistors, a common test signal line (GF) that routes to the array, stating “GF: the G end of each DUT is connected to the GF signal line, it can be used to force corresponding voltage to G end,” and illustrates that this connection from the common GF line to the multiple respective control nodes is achieved through a set of respective switches (SGF), which constitutes the “set of coupling channels,” in Fig. 12; [0024, [0082], & [099]-[0100]. A POSITA would have found it obvious to apply the addressable, multi-transistor array architecture of Pan to the stress testing framework of Jang and Zeng. By combining Zeng’s dedicated stress voltage generation with Pan’s centralized test signal routing (GF line and SGF switches), the resulting circuit inherently couples to a first end of each coupling channel to a common test node, and a second end to the control node of a respective electronic switch in the set.
Applicant in their submitted response, see pg. 11 of Applicant remarks, presents the fourth argument that the art reference(s) Jang (US2008/0295605), in view of Zeng (US2015/0381148), and further in view of Neidorff (US2020/0200815), as cited by the Applicant, do not teach, suggest, and/or disclose individually or in combination, “wherein the set of coupling channels is configured to propagate application of the stress test voltage from the common test node to the respective control node of the electronic switches in the set of electronic switches,” of amended independent claim 1 and similarly amended independent claims 8 & 15.
The Examiner respectfully disagrees and would like break the argument presented into two parts. The first part the Examiner would like to highlight is how prior art references Jang (US2008/0295605), in view of Zeng (US2015/0381148), in view of Neidorff (US2020/0200815), and in light of the amendments, further in view of Pan (US2017/0059645A1), read on “the set of coupling channels is configured to propagate application of the stress test voltage from the common test node to the respective control node of the electronic switches in the set of electronic switches,” which was previously presented in the Non-Final OA (pp.3-9) prior to amendments. The Applicant mentions that prior art reference Zeng applies the “stress voltage (Vst)” directly to “the gate terminal by a stress voltage generator 32,” rather than propagating it from “the VarREF node 124.” The Examiner appreciates the explanation and additional evidence; however it is noted that a combination rejection cannot be overcome by arguing that the secondary reference (Zeng) alone fails to teach a specific limitation. The proper test is whether the combined teachings of the prior art would have suggested the claimed invention to a POSITA. Please refer to MPEP 2145(IV). Applicant’s reply fails to address the combined teaching of the applied references and instead argues that the secondary reference individually does not teach all of the claim limitations. The second part the Examiner would like to highlight is new prior art reference, Pan et al. (US2017/0059645A1), in light of the amendments in claim 1, further reads on the claim language limitation(s). Pan teaches an addressable test circuit having a common test signal line GF that connects to the control nodes “G end” of multiple electronic switches (DUTs) via respective switches SGF, stating “GF: the end of each DUT is connected to GF signal line, it can be used to force corresponding voltage to G end.” A POSITA modifying the test block of Jang with the centralized addressing of Pan and the stress-testing parameters of Zeng, would utilize Pan’s common test node GF to route and propagate the test voltage. In this combined circuit, the GF line functions as the common test node, and the SGF switches, act as the coupling channels configured to propagate the application of the stress test voltage from the common node to the respective control nodes.
Applicant in the submitted amended claims, received June 4, 2026, not mentioned in the remarks, includes new amended claim language limitations in amended independent claim 1, and “sensing, at the first input nodes of the set of comparator circuits, a set of control voltages comprising each control voltage sensed at the respective control node of the respective one of the electronic switches in the set of electronic switches.” In light of the amendment(s), a new ground(s) of rejection(s) have been made in view of Pan et al. (US2017/0059645A1).
Therefore, based on the reasoning provided above, the rejection(s) of amended independent claims 1, 8, & 15, and dependent claims 2-7, 9-14, & 16-20, which depend from and incorporate the limitations of amended independent claims 1, 8, & 15, are respectively maintained. Rejections based on the newly cited prior art reference(s) follow.
The Applicant has further presented a set of arguments, pointing out their rationale of how the prior art reference(s) made of record in the most recent Non-Final Office Action, mailed March 5, 2026, do not reach, suggest, and/or disclose the currently amended independent claim 8 limitations, “a set of coupling channels, each coupling channel having a first end coupled to a common test node and a second end coupled to the respective control node of a respective one of the electronic switches,” “a stress voltage supply source coupled to the common test node,” and “a set of comparator circuits, each comparator circuit having a first input node coupled, via the sensing circuitry, to the respective control node of the respective one of the electronic switches in the set of electronic switches and having a second input node coupled to the threshold voltage node.”
Applicant in their submitted response, see pp. 11-12 of Applicant remarks, presents the first argument that the prior art reference(s) Jang (US2008/0295605), in view of Zeng (US2015/0381148), do not teach, suggest, and/or disclose, “a set of coupling channels, each coupling channel having a first end coupled to a common test node and a second end coupled to the respective control node of a respective one of the electronic switches,” of amended independent claim 8 and similarly amended independent claims 1 & 15.
The Examiner respectfully disagrees and would like break the argument presented into two parts. The first part the Examiner would like to highlight is how prior art references Jang (US2008/0295605), in view of Zeng (US2015/0381148), , in light of the amendments, further in view of Pan (US2017/0059645A1), read on “a set of coupling channels, each coupling channel having a first end coupled to a common test node and a second end coupled to the respective control node of a respective one of the electronic switches,” which was previously presented in the Non-Final OA (pp.26-28) prior to amendments. The Applicant mentions that “the Office Action maps the transistors T11, T12, T13, and T14 of the detection signal generation circuit 400 to the electronic switches rather than the transistors TR1-TR3…” on pg. 12. The first part the Examiner would like to highlight is to clarify that the previous office action mapped these claim language limitations to secondary art reference Zeng and not primary art reference Jang, therefore there is insufficient explanation of rationale on how the secondary art reference mapped the claim language limitations in error. Applicant remarks don’t specifically mention any prior art reference on pp. 11-12 of Applicant remarks regarding independent claim 8 mapping. Therefore, the remarks do not provide any specific reasons, but rather generalizations not tied to the facts of the application, as to why either the findings of fact or the legal conclusion of obviousness in the rejection of secondary art reference Zeng is allegedly in error. Please refer to MPEP 2143(I), 2143.02(I), and 2143.02(II). Further, a combination rejection cannot be overcome by arguing, not mentioning which reference alone and/or in combination, fail to teach a specific limitation. The proper test is whether the combined teachings of the prior art would have suggested the claimed invention to a POSITA. Please refer to MPEP 2145(IV). Applicant’s reply fails to address the combined teaching of the applied references and instead argues that the claim limitations are not taught. The second part the Examiner would like to highlight is the additional prior art reference, Pan et al. (US2017/0059645A1), in light of the amendments in claim 8, further read on the claim language limitation(s). Pan teaches an addressable array of electronic switches (DUTs), a common test signal line (GF), stating “GF: the G end of each DUT is connected to GF signal line, it can be used to force corresponding voltage to G end,” and illustrates this connection from the common GF node to the respective control nodes “G end” is achieved through respective switches (SGF), in Fig. 9D; [0024] & [0082]-[0084]. If re-mapped to the primary art reference, the transistors T11-T14 of Jang are part of the detection/comparator circuit used to evaluate the switches, not the switches themselves. Further, the gates of T11-T14 receive inputs like Spp and VRn and comparator 411 connects to drain-side nodes in Fig. 1. A POSITA would have found it obvious to apply the multi-transistor addressing architecture of Pan to the stress testing framework of Jang. In the modified circuit, the GF line functions as the common test node, and the SGF switches act as the coupling channels, ensuring that a first end of each coupling channel is coupled to the common test node and a second end is coupled to the respective control node of the electronic switches.
Applicant in their submitted response, see pp. 11-12 of Applicant remarks, presents the first argument that the prior art reference(s) Jang (US2008/0295605), in view of Zeng (US2015/0381148), do not teach, suggest, and/or disclose, “a stress voltage supply source coupled to the common test node,” of amended independent claim 8 and similarly amended independent claims 1 & 15.
The Examiner respectfully disagrees and would like break the argument presented into two parts. The first part the Examiner would like to highlight is how prior art references Jang (US2008/0295605), in view of Zeng (US2015/0381148, in light of the amendments, further in view of Pan (US2017/0059645A1), read on “a stress voltage supply source coupled to the common test node,” which was previously presented in the Non-Final OA (pp.26-28) prior to amendments. The Applicant mentions that “the Office Action maps the transistors T11, T12, T13, and T14 of the detection signal generation circuit 400 to the electronic switches rather than the transistors TR1-TR3…” on pg. 12. The first part the Examiner would like to highlight is to clarify that the previous office action mapped these claim language limitations to secondary art reference Zeng and not primary art reference Jang, therefore there is insufficient explanation of rationale on how the secondary art reference mapped the claim language limitations in error. Applicant remarks don’t specifically mention any prior art reference on pp. 11-12 of Applicant remarks regarding independent claim 8 mapping. Therefore, the remarks do not provide any specific reasons, but rather generalizations not tied to the facts of the application, as to why either the findings of fact or the legal conclusion of obviousness in the rejection of secondary art reference Zeng is allegedly in error. Please refer to MPEP 2143(I), 2143.02(I), and 2143.02(II). Further, a combination rejection cannot be overcome by arguing, not mentioning which reference alone and/or in combination, fail to teach a specific limitation. The proper test is whether the combined teachings of the prior art would have suggested the claimed invention to a POSITA. Please refer to MPEP 2145(IV). Applicant’s reply fails to address the combined teaching of the applied references and instead argues that the claim limitations are not taught. The second part the Examiner would like to highlight is the additional prior art references, Pan et al. (US2017/0059645A1), in light of the amendments in claim 8, Jang (US2008/0295605) and Zeng (US2015/0381148), further read on the claim language limitation(s). Clarifying, that the electronic switches are the transistors of Jang’s function block, or the DUTs in the Pan/Zeng combination. The rejection could be further amended to clarify that the comparison is performed by the detection of Jang while the stressing and gate-side coupling are performed by the structures in Zeng and Pan. Zeng explicitly teaches a ”stress voltage generator 32” in Fig. 1B; [0017]. When Zeng’s “stress voltage generator 32” is incorporated into the addressable routing architecture of Pan, it functions as ”a stress voltage supply source coupled to the common test node.” A POSITA would have found it obvious to modify the function block of Jang with the centralized addressing and testing architecture of Pan, utilizing the stress voltage generator of Zeng. In the combined, modified circuit, the control nodes (gates) of the electronic switches (TR1-TR3) would be coupled to a common test node (GF) to receive a uniform stress test voltage during the test mode.
Applicant in their submitted response, see pp. 11-12 of Applicant remarks, presents the first argument that the prior art reference(s) Jang (US2008/0295605), in view of Zeng (US2015/0381148), do not teach, suggest, and/or disclose, “a set of comparator circuits, each comparator circuit having a first input node coupled, via the sensing circuitry, to the respective control node of the respective one of the electronic switches in the set of electronic switches and having a second input node coupled to the threshold voltage node,” of amended independent claim 8 and similarly amended independent claims 1 & 15.
The Examiner respectfully disagrees and would like break the argument presented into two parts. The first part the Examiner would like to highlight is how prior art references Jang (US2008/0295605), in view of Zeng (US2015/0381148, in light of the amendments, further in view of Pan (US2017/0059645A1), read on “a set of comparator circuits, each comparator circuit having a first input node coupled, via the sensing circuitry, to the respective control node of the respective one of the electronic switches in the set of electronic switches and having a second input node coupled to the threshold voltage node.” which was previously presented in the Non-Final OA (pp.26-28) prior to amendments. The Applicant mentions that “the Office Action maps the transistors T11, T12, T13, and T14 of the detection signal generation circuit 400 to the electronic switches rather than the transistors TR1-TR3…” on pg. 12. The first part the Examiner would like to highlight is to clarify that the previous office action mapped these claim language limitations to primary art reference Jang. Applicant remarks don’t specifically mention any prior art reference on pp. 11-12 of Applicant remarks regarding independent claim 8 mapping. Further, a combination rejection cannot be overcome by arguing, not mentioning which reference alone and/or in combination, fail to teach a specific limitation. The proper test is whether the combined teachings of the prior art would have suggested the claimed invention to a POSITA. Please refer to MPEP 2145(IV). Applicant’s reply fails to address the combined teaching of the applied references and instead argues that the claim limitations are not taught. The second part the Examiner would like to highlight is Jang (US2008/0295605) and Zeng (US2015/0381148), further in view of the additional prior art reference, Pan et al. (US2017/0059645A1), in light of the amendments in claim 8, further read on the claim language limitation(s). The Applicant correctly notes that transistors T11-T14 of Jang are components of the detection signal generation circuit 400 and not the electronic switches undergoing testing. The Examiner would like to clarify that the claimed “set of electronic switches” maps to the transistors TR1-TR3 of Jang’s function block, or the explicit DUTs in Pan. Pan teaches a dedicated sense signal line, designated as GL, which connects directly to the control node, “the G end” of the transistor, stating the functional purpose of this connection “GL: sensing actual voltage of the selected transistor’s G end,” and illustrating the direct gate-side sensing is achieved via selectively activated switches (SGL), which act as the “sensing circuitry” connecting the control node to the sensing line, in Fig. 1B; [0025] & [0099]-[0100]. A POSITA would have found it obvious to modify the detection architecture of Jang with the gate-sensing topology taught by pan. This combined circuit, the sensing circuitry (GL sense line and SGL switches of Pan) couple the first input node of Jang’s comparator circuits directly to the respective control node (gate) of the electronic switches. The second input node remains coupled to the threshold voltage node (VRp/VRn) as taught by Jang, Fig. 3; [0016]-[0017], [00054], & [0062]. The motivation to combine these teaches is to sense the actual voltage directly at the gate terminal, avoiding measurement inaccuracies caused by intermediate components or drain-side voltages.
Therefore, based on the reasoning provided above, the rejection(s) of amended independent claims 8, 1, & 15, and dependent claims 9-14, 2-7, & 16-20, which depend from and incorporate the limitations of amended independent claims 8, 1, & 15, are respectively maintained. Rejections based on the newly cited prior art reference(s) follow.
The Applicant has further presented a set of arguments, pointing out their rationale of how the prior art reference(s) made of record in the most recent Non-Final Office Action, mailed March 5, 2026, do not reach, suggest, and/or disclose the currently amended independent claim 15, and similarly amended independent claims 1 & 15 limitations, “a set of coupling channels, each coupling channel having a first end coupled to a common test node and a second end coupled to the respective control node of a respective one of the electronic switches in the set of electronic switches, wherein the set of coupling channels are configured to propagate application of the stress test voltage from the common test node to the respective control node of each electronic switch in the set of electronic switches,” and “a set of comparator circuits having a first input node couples, via the sensing circuitry, to the respective control node of the respective one of the electronic switches in the set of electronic switches and having a second input node coupled to the threshold voltage node.” Applicant’s arguments have been fully considered but they are not persuasive. In light of the amendment(s), a new ground(s) of rejection(s) have been made in view of Pan et al. (US2017/0059645A1).
Applicant in their submitted response, see pp. 11-13 of Applicant remarks, presents the first argument that the prior art reference(s) Jang (US2008/0295605), in view of Zeng (US2015/0381148), and further in view of Neidorff (US2020/0200815), as cited by the Applicant, do not teach, suggest, and/or disclose individually or in combination, “a set of coupling channels, each coupling channel having a first end coupled to a common test node and a second end coupled to the respective control node of a respective one of the electronic switches in the set of electronic switches, wherein the set of coupling channels are configured to propagate application of the stress test voltage from the common test node to the respective control node of each electronic switch in the set of electronic switches,” of amended independent claim 15 and similarly amended independent claims 1 & 8.
The Examiner respectfully disagrees and would like break the argument presented into two parts. The first part the Examiner would like to highlight is how prior art references Jang (US2008/0295605), in view of Zeng (US2015/0381148), in view of Neidorff (US2020/0200815), in light of the amendments, further in view of Pan (US2017/0059645A1), read on “a set of coupling channels, each coupling channel having a first end coupled to a common test node and a second end coupled to the respective control node of a respective one of the electronic switches in the set of electronic switches, wherein the set of coupling channels are configured to propagate application of the stress test voltage from the common test node to the respective control node of each electronic switch in the set of electronic switches,” which was previously presented in the Non-Final OA (pp.19-23) prior to amendments. The Applicant mentions that “for similar reason as discussed regarding claims 1 and 8, Applicant respectfully submits that the prior art references do not teach or suggest the limitations of claim 15,“ on pg. 13, and a bit signal ADDi applied to the gates of TR1 and TR3 and a high voltage VPP applied to the gate of the transistor TR2” on pg. 10, no additional evidence or rational is provided in regard to why the primary reference does not teach the claim language limitations. The first part the Examiner would like to highlight is there is insufficient explanation of rationale. The remarks do not provide any specific reasons, but rather generalizations not tied to the facts of the application, as to why either the findings of fact or the legal conclusion of obviousness in the rejection is allegedly in error. Please refer to MPEP 2143(I), 2143.02(I), and 2143.02(II). Further, a combination rejection cannot be overcome by arguing that the primary reference alone fails to teach a specific limitation. The proper test is whether the combined teachings of the prior art would have suggested the claimed invention to a POSITA. Please refer to MPEP 2145(IV). Applicant’s reply fails to address the combined teaching of the applied references and instead argues that the primary reference individually does not teach all of the claim limitations. The second part the Examiner would like to highlight is the additional prior art references, Pan et al. (US2017/0059645A1), in light of the amendments in claim 15, and Zeng (US2015/0381148), further read on the claim language limitation(s). Pan teaches an addressable, multi-transistor array routing test circuit where the gate (G) end of each transistor under test (DUT) is connected to a common test signal line (GF) through respective switches (SGF), and states that the common (GF) signal line is used to “force corresponding voltage to G end,” in Fig. 9D; [0024] & [0082]-[0084]. Zeng teaches utilizing a dedicated stress voltage generator to apply a “stress voltage” directly to a gate terminal during a testing mode, Fig. 1B; [0017]. A POSITA would have found it obvious to apply the addressable, multi-transistor array routing architecture of Pan to the stress testing framework and the function block of Jang. By combining Zeng’s dedicated stress voltage generator with Pan’s centralized test signal routing (GF line and the SGF switches), the resulting circuit inherently couples a first end of each coupling channel to a common test node, and a second end to the control node of a respective electronic switch in the set to propagate the stress test voltage.
Applicant in their submitted response, see pp. 11-13 of Applicant remarks, presents the first argument that the prior art reference(s) Jang (US2008/0295605), in view of Zeng (US2015/0381148), and further in view of Neidorff (US2020/0200815), as cited by the Applicant, do not teach, suggest, and/or disclose individually or in combination, “a set of comparator circuits having a first input node couples, via the sensing circuitry, to the respective control node of the respective one of the electronic switches in the set of electronic switches and having a second input node coupled to the threshold voltage node.” of amended independent claim 15 and similarly amended independent claims 1 & 8.
The Examiner respectfully disagrees and would like break the argument presented into two parts. The first part the Examiner would like to highlight is how prior art references Jang (US2008/0295605), in view of Zeng (US2015/0381148, in view of Neidorff (US2020/0200815), in light of the amendments, further in view of Pan (US2017/0059645A1), read on “a set of comparator circuits having a first input node couples, via the sensing circuitry, to the respective control node of the respective one of the electronic switches in the set of electronic switches and having a second input node coupled to the threshold voltage node.” which was previously presented in the Non-Final OA (pp.19-23) prior to amendments. The Applicant mentions that “for similar reason as discussed regarding claims 1 and 8, Applicant respectfully submits that the prior art references do not teach or suggest the limitations of claim 15,“ on pg. 13, and “the Office Action maps the transistors T11, T12, T13, and T14 of the detection signal generation circuit 400 to the electronic switches rather than the transistors TR1-TR3…” on pg. 12. The first part the Examiner would like to highlight is to clarify that the previous office action mapped these claim language limitations to primary art reference Jang. Applicant remarks don’t specifically mention any prior art reference on pp. 11-13 of Applicant remarks regarding independent claim 15 mapping. Further, a combination rejection cannot be overcome by arguing, not mentioning which reference alone and/or in combination, fail to teach a specific limitation. The proper test is whether the combined teachings of the prior art would have suggested the claimed invention to a POSITA. Please refer to MPEP 2145(IV). Applicant’s reply fails to address the combined teaching of the applied references and instead argues that the claim limitations are not taught. The second part the Examiner would like to highlight is Jang (US2008/0295605) and Zeng (US2015/0381148), in view of Neidorff (US2020/0200815), further in view of the additional prior art reference, Pan et al. (US2017/0059645A1), in light of the amendments in claim 15, further read on the claim language limitation(s). The Applicant correctly notes on pg. 12, in regard to independent claim 8, which is similar to independent claim 15, that transistors T11-T14 of Jang are components of the detection signal generation circuit 400 and not the electronic switches undergoing testing. The Examiner would like to clarify that the claimed “set of electronic switches” maps to the transistors TR1-TR3 of Jang’s function block, or the explicit DUTs in Pan. Pan teaches a dedicated sense signal line, designated as GL, which connects directly to the control node, “the G end” of the transistor, stating the functional purpose of this connection “GL: sensing actual voltage of the selected transistor’s G end,” and illustrating the direct gate-side sensing is achieved via selectively activated switches (SGL), which act as the “sensing circuitry” connecting the control node to the sensing line, in Fig. 1B; [0025] & [0099]-[0100]. A POSITA would have found it obvious to modify the detection architecture of Jang with the gate-sensing topology taught by Pan. This combined circuit, the sensing circuitry (GL sense line and SGL switches of Pan) couple the first input node of Jang’s comparator circuits directly to the respective control node (gate) of the electronic switches. The second input node remains coupled to the threshold voltage node (VRp/VRn) as taught by Jang, Fig. 3; [0016]-[0017], [00054], & [0062]. The motivation to combine these teaches is to sense the actual voltage directly at the gate terminal, avoiding measurement inaccuracies caused by intermediate components or drain-side voltages.
Therefore, based on the reasoning provided above, the rejection(s) of amended independent claims 15, 1, & 8, and dependent claims 16-20, 2-7, & 9-14, which depend from and incorporate the limitations of amended independent claims 15, 1, & 8, are respectively maintained. Rejections based on the newly cited prior art reference(s) follow.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 14, & 16 are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al. (US 2008/0295605 A1, Pub. Date Dec. 4, 2008, hereinafter, Jang), in view of Zeng (US 2015/0381148 A1, Pub. Date Dec. 31, 2015, hereinafter, Zeng), in view of Neidorff et al. (US 2020/0200815 A1, Pub. Date Jun. 25, 2020, hereinafter, Neidorff), and further in view of Pan et al. (US 2017/0059645 A1, Pub. Date Mar. 2, 2017, hereinafter, Pan).
Regarding independent claim 1, Jang, teaches:
A method, comprising ([Title], [Abstract] & [0014]-[0020]: provides the foundational method of stress testing):
providing a set of electronic switches having a current path between a supply node and ground, wherein each electronic switch in the set of electronic switches comprises a respective control node to receive a stress test voltage (Fig. 1; [0009], [0050] & [0059]-[0062]: provides the transistors TR1-TR3 mapping to the electronic switches, drain-source paths (current paths) coupled through the high voltage VPP and ground, which acts as the supply node, and the gates, which act as the control nodes receiving the stress voltage);
providing a threshold voltage level to a second input node of each comparator circuit of the set of comparator circuits (Fig. 3; [0016]-[0017], [0054] & [0062]: teaches providing threshold/reference voltages (VRp/VRn) to input nodes of comparator circuitry);
performing a set of comparisons of the set of control voltages and the threshold voltage level (Fig. 4; [0062]-[0071] & [0087]-[0091]: teaches mathematical comparisons against voltages and reference thresholds);
producing a set of comparison signals, each comparison signal having the first logic value in response to the control voltage sensed at the respective control node exceeding the threshold voltage level (Fig. 4; [0062]-[0071] & [0087]-[0091]: comparators output binary logic values based on whether the threshold is exceed or not) and a second logic value in response to the control voltage sensed at the respective control node failing to exceed the threshold voltage level (Fig. 4; [0062]-[0071] & [0087]-[0091]: teaches comparators performing mathematical comparisons against reference thresholds to output logic values (0 or 1, representing logic low or high) based on whether the threshold is exceeded);
Jang, in combination with Zeng, and Neidorff, are silent in regard to:
coupling a first end of each coupling channel of a set of coupling channels to a common test node and a second end of each coupling channel of the set of coupling channels to the control node of a respective one of the electronic switches in the set of electronic switches, wherein the set of coupling channels is configured to propagate application of the stress test voltage from the common test node to the respective control node of the electronic switches in the set of electronic switches;
based on a calibration enable signal having a first logic value, coupling a first input node of each comparator circuit of a set of comparator circuits to the control node of respective one of the electronic switches in the set of electronic switches;
sensing, at the first input nodes of the set of comparator circuits, a set of control voltages comprising each control voltage sensed at the respective control node of the respective one of the electronic switches in the set of electronic switches;
However, Pan, further teaches:
coupling a first end of each coupling channel of a set of coupling channels to a common test node and a second end of each coupling channel of the set of coupling channels to the control node of a respective one of the electronic switches in the set of electronic switches, wherein the set of coupling channels is configured to propagate application of the stress test voltage from the common test node to the respective control node of the electronic switches in the set of electronic switches (Fig. 9D; [0024], [0082], & [0084]: teaches an addressable array where a common test node GF connects via coupling channels (switches SGF) directly to the control nodes (gates) to propagate the forced voltage);
It would have been obvious to one of ordinary skill before the effective filing date to apply Pan’s centralized force and sense signal lines and switching topology to the stress detection architecture of Jang as a substitution of known gate-level sensing techniques to improve similar devices. Pan teaches an addressable test circuit utilizing a common force signal line GF coupled to the gate G end of each transistor under test via switches SGF acting as coupling channels, and a dedicated sense signal line GL and switches SGL connected directly to the gate to act as sensing circuitry, sensing the control node voltage. The motivation to combine these references is to solve the problem of measurement inaccuracies caused by intermediate voltage drops across source/drain regions, providing the benefit of accurate, direct gate-level stress application and sensing. This represents the use of a known technique to improve similar devices, providing direct gate-level stress application and sensing. This combination yields the predictable results of an accurate array of test switches receiving and sensing a stress test voltage directly at the control nodes (KSR).
However, Jang, in combination with Pan, further teach:
based on a calibration enable signal having a first logic value, coupling a first input node of each comparator circuit of a set of comparator circuits to the control node of respective one of the electronic switches in the set of electronic switches (Jang: [0009], [0026], [0036], [0050]-[0052], [0054]-[0066], & [0077]: teaches using test mode enable signals and switching units to selectively activate/couple the sensing and detection circuitry to the function block specifically during the test mode. The test mode enables signal maps to the “enable calibration signal having a first logic value”; Pan: [0025], [0084], & [0099]: teaches a dedicated sense line GL coupled directly to the gate (control node) via selection switches bypassing the drain-side nodes)
sensing, at the first input nodes of the set of comparator circuits, a set of control voltages comprising each control voltage sensed at the respective control node of the respective one of the electronic switches in the set of electronic switches (Jang: [0062]-[0064]: first input nodes (i.e., N11/N12 and N21/N22) of the comparators sense the voltage drops corresponding to the control/stress states of the transistors; Pan: [0025] & [0084]: utilizing Pan’s GL line routing, the comparator’s first input nodes physically sense the actual control voltage directly at the respective control node (gate));
It would have been obvious to one of ordinary skill before the effective filing date to apply Pan’s centralized force and sense signal lines and switching topology to the stress detection architecture of Jang. While Jang teaches testing a function block with transistors and comparators sensing drain-side nodes, Pan teaches an addressable test circuit by utilizing a common force signal line GF coupled to the gate G end of each transistor under test via switches acting as coupling channels, and a dedicated sense signal line GL connected directly to the gate to accurately sense the control node voltage. The motivation to combine these references is to solve the problem of measurement inaccuracies caused by intermediate voltage drops across source/drain regions, providing the benefit of accurate, direct gate-level stress application and sensing. This represents the use of a known technique to improve similar devices, yielding the predictable results of an accurate array of test switches receiving and sensing a stress test voltage from a shared centralized source (KSR).
Jang, is silent in regard to:
applying the stress test voltage to the common test node;
However, Zeng, further teaches:
applying the stress test voltage to the common test node (Fig. 1B; [0017] & [0030]: teaches the step of applying a dedicated stress voltage (Vst) from a generator);
It would have been obvious to one of ordinary skill before the effective filing date to utilize the dedicated stress voltage generator of Zeng as the voltage source applied to the common test node GF of Pan’s adapted architecture. Jang and Pan teach forcing a generalized voltage to the control nodes via a common test line GF. Zeng teaches applying a dedicated stress voltage (Vst) from a specific stress voltage generator 32 directly to a floating gate terminal of a power transistor 12 to execute a dedicated gate stress testing mode. This substitution solves the problem of inadequately stressing power devices, providing the benefit of ensuring the applied test voltage is calibrated to exceed normal operational thresholds for proper testing. Combining these references yields the predictable result of a comprehensive testing architecture capable of safely and effectively executing a high-voltage gate stress testing mode (KSR).
Jang, in combination with Zeng, are silent in regard to:
in response to at least one comparison signal in the set of comparison signals having the second logic value, increasing the stress test voltage applied at the common test node;
in response to each and every comparison signal in the set of comparison signals having the first logic value, interrupting performing the set of comparisons; and
providing a value reached by the stress test voltage applied at the common test node as a calibrated stress test voltage value to a user circuit.
However, Neidorff, further teaches:
in response to at least one comparison signal in the set of comparison signals having the second logic value , increasing the stress test voltage applied at the common test node (Fig. 7; [0002], [0040]-[0042], & [Claim 9]: teaches performing an ascending sweep (increasing the test voltage) while continually checking if a threshold has been met, while the threshold is not met (the comparison signal has the second/failing logic value), the voltage continues to incrementally increase);
in response to each and every comparison signal in the set of comparison signals having the first logic value, interrupting performing the set of comparisons (Fig. 7; [0002], [0040]-[0042], & [Claim 9]: teaches interrupting (stopping) so the value can be identified, the sweeping and comparison loop the exact moment the threshold logic condition is satisfied (the first logic value is reached)); and
providing a value reached by the stress test voltage applied at the common test node as a calibrated stress test voltage value to a user circuit ([0029] & [0040]-[0043]: the identified voltage from the interrupted sweep is designated as the threshold/calibrated limit, and this information is provided to a downstream controller/output (user circuit) to a display or external device).
It would have been obvious to one of ordinary skill before the effective filing date to incorporate the ascending voltage sweep algorithm of Neidorff into the integrated test circuits of Jang, Zeng, and Pan. Jang, Pan, and Zeng teach applying a static stress voltage and outputting comparison logic values but lack an iterative ascending sweep algorithm designed to find a definitive calibration limit. Neidorff teaches a parametric test method where a controller iteratively increases a test voltage in an ascending sweep, interrupts the sweep when a threshold level corresponding to a specific logic state is reached, and provides the identified threshold voltage as a calibrated value on an output to test equipment. The motivation to combine these teachings is to solve the problem of applying arbitrary static stress voltages that could destroy components, thereby providing the benefit of safely and dynamically pinpointing the exact limits of the switches. This combination utilizes a known technique to improve similar devices, yield the predictable results of an accurate parametric calibration loop that prevents catastrophic device over-stress while outputting verified calibration data (KSR).
Regarding dependent claim 2, Jang, teaches:
The method of claim 1, comprising ([Title], [Abstract] & [0014]-[0020]):
coupling a supply voltage level at one end of a series arrangement of resistive elements referred to ground thereby providing the threshold voltage level at a node intermediate the series arrangement ([0049]-[0054]: teaches the method of providing the threshold voltage (Snn) using a voltage divider circuit including a plurality of resistors. Implementing a voltage divider requires coupling a supply voltage at one end of a series of resistors to ground and tapping the divided threshold voltage at an intermediate node), wherein resistive elements in the at least one resistive voltage divider have resistance values based on resistance values of resistive elements in the series arrangement of resistive elements coupled to the supply voltage level (Figs. 2-3; [0026], [0036],[0050]-[0052], [0054]-[0067], [0069]-[0071], [0087], [Claim 11] & [Claim 20]: teaches using resistors in both the threshold generation path (voltage divider for Snn) and the sensing paths (R11/R12 and R21/R22). Even though the mathematical ratio is not stated that R11/R12 are sized based on the resistors in the Snn voltage divider sizing resistors proportionately or matching them across reference and sensing circuits to cancel out system errors (i.e., thermal drift and process variations) is a well-known design parameter optimization in the art).
It is recognized that the citations and evidence above are derived from potentially different embodiments of a single reference. Nevertheless, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to employ combinations and sub-combinations of these complementary embodiments. Jang teaches generating a reference threshold voltage via a “voltage divider circuit including a plurality of resistors,” which structurally dictates a series arrangement of resistive elements coupled between a supply voltage and ground, and comparing it against a sensing path that also utilizes resistors (R11, R12, R21, R22) to determine voltage drops. A POSITA would inherently recognize that if the resistance values of the reference divider are not based on (e.g., scaled to or matched with) resistance values of the sensing divider, any temperature variations or manufacturing process discrepancies would cause the resistance values to drift independently, leading to false stress failure detections. In analog CMOS and semiconductor circuit design, it is standard practice to construct reference voltage dividers and sensing voltage dividers using matched or proportionally scaled resistive elements. Further, resistance values in a reference divider must be proportionately sized based on the sensing resistors to maintain accuracy across the comparison circuit. The motivation to match these values is to solve the problem of false comparator logic readings, yielding the benefit canceling out thermal drift and semiconductor process variations. Therefore, it would have been an obvious design choice to a POSITA to select the resistance values in the reference series arrangement based on the values in the sensing resistive divider, ensuring accuracy and stability across environmental and manufacturing variables, that would otherwise motivate experimentation and optimization, and doing so merely combines prior art elements to improve similar devices, ensuring the test circuit remains stable and accurate under varying environmental conditions, according to known methods to yield predictable results (KSR).
Jang, in combination with Zeng, and Neidorff, are silent in regard to:
in response to the calibration enable signal having the first logic value, coupling at least one resistive voltage divider to control nodes of the electronic switches in the set of electronic switches to sense the control voltages via the at least one resistive voltage divider; and
However, Jang, in combination with Pan, further teach:
in response to the calibration enable signal having the first logic value, coupling at least one resistive voltage divider to control nodes of the electronic switches in the set of electronic switches to sense the control voltages via the at least one resistive voltage divider (Jang: [0026], [0036],[0050]-[0052], [0054], [0058]-[0067], [0069]-[0071], [0087], [Claim 11] & [Claim 20]: test mode activation signal (TM) maps to the calibration enable signal. When activated, the test circuitry is coupled. Teaches using resistors (R11, R12, etc.) to sense the voltage drops corresponding to the control/stress states. Utilizing these resistors to sense a voltage drops structurally acts as sensing via a resistive voltage divider; Pan: Fig. 12; [0025] & [0099]-[0100]: teaches a dedicated sense line GL coupled directly to the control nodes (gates) via selectively enabled switches); and
It would have been obvious to one of ordinary skill before the effective filing date to apply the direct gate-sensing routing of Pan to the resistive sensing architecture of Jang. While Jang teaches utilizing a test mode enable signal to couple resistive sensing circuitry to the device, it lacks direct coupling to the actual control nodes (gates) of the switches. Pan teaches an addressable array where a dedicated sense line GL is coupled directly to the gate (control node) via a switch SGL to sense the control voltage. The motivation for this substitution is to solve the measurement inaccuracies caused by intermediate components, such as voltage drops across source/drain regions, providing the benefit of accurate, direct gate-level voltage sensing. This combination utilizes a known technique to improve similar devices, yielding the predictable results of a test circuitry that directly senses actual control node voltages using resistive sensing elements (KSR).
Regarding dependent claim 3, Jang, teaches:
The method of claim 1 ([Title], [Abstract], & [0014]-[0020]), wherein the set of electronic switches (Fig. 1; [0009]: discloses the set of electronic switches (plurality of transistors TR1-TR3)) wherein the current path is configured to be made at least partially conductive or non-conductive based on a logic value of the control signal (Fig. 1; [0005]-[0009] & [0077]: teaches that the switches are MOSFETs and applying a logic value such as a “selectively activated” bit signal to the gate of a MOSFET makes the source-to-drain current path conductive (on) or non-conductive (off)).
Jang, is silent in regard to:
is coupled to a set of driving circuits and wherein control nodes of electronic switches in the set of electronic switches are coupled to an output node of a respective driving circuit in the set of driving circuits, each control node configured to receive a control signal from a respective driving circuit of the set of driving circuits,
However, Zeng, further teaches:
is coupled to a set of driving circuits (Fig. 2; [0018]-[0022]: discloses the blueprint for the driving circuit (VGS generator circuit 120) that is coupled switches to operate them) and wherein control nodes of electronic switches in the set of electronic switches are coupled to an output node of a respective driving circuit in the set of driving circuits (Fig. 2; [0018]-[0024]: gate (G) terminal maps to the control node of the electronic switch, the control signal line 118 exiting the VGS generator circuit maps to the output node of the respective driving circuit), each control node configured to receive a control signal from a respective driving circuit of the set of driving circuits (Fig. 2; [0018]-[0024]: establishes that the control node (gate) is configured to receive the gate control signal originating from the driving circuit (VGS generator)),
It would have been obvious to one of ordinary skill before the effective filing date to apply the driving circuit architecture taught by Zeng to the array of transistor switches, where the switches are activated by logical bit signals, taught by Jang to actively control them during normal and test modes (i.e., stress test mode). Zeng details a VGS generator circuit (driving circuit) that has an output node coupled directly to the gate terminal (control node) of a transistor (electronic switch) to deliver a logic-based gate control signal that drives the transistor “on/off” (conductive/non-conductive). A POSITA would be motivated and recognize that to implement Jang’s array of test switches within a method of operation, one must drive the switches between conductive and non-conductive states during normal operation. Therefore, it would be obvious to incorporate a set of driving circuits, as taught by Zeng, coupled to the respective control nodes of the transistors in Jang’s array, where the combination of prior art reference elements would yield predictable results (KSR), of a properly functioning switch array where the current path is made conductive or non-conductive based on the logic value of the driver’s control signal.
Regarding dependent claim 4, Jang, teaches:
The method of claim 1 ([Title], [Abstract], & [0014]-[0020]), wherein electronic switches in the set of electronic switches comprise transistors (Fig. 1; [0009]).
Regarding dependent claim 5, Jang, teaches:
The test circuit of claim 1 ([Title], [Abstract], & [0014]-[0020]), wherein electronic switches in the set of electronic switches comprise MOSFET transistors ([0005]-[0007], [0009], & [0077]).
Regarding dependent claim 6, Jang, teaches:
The method of claim 1 ([Title], [Abstract] & [0015]-[0020]),
Jang, in combination with Zeng, are silent in regard to:
wherein increasing the stress test voltage comprises step-wise increasing the stress test voltage starting from a minimum voltage level to a maximum voltage level.
However, Neidorff, further teaches:
wherein increasing the stress test voltage comprises step-wise increasing the stress test voltage starting from a minimum voltage level to a maximum voltage level (Fig. 5; [0040]-[0043]: teaches using a processor to apply multiple voltages in an ascending sweep, where by definition, a digital processor sweeping a voltage upwards inherently does so in discrete increments (“step-wise”). An ascending sweep inherently dictates starting from a lower starting bound (“minimum voltage level”) and sweeping upwards until either the threshold is met or an upper safety bound (“maximum voltage level”) is reached to prevent uncontrolled destruction of the device and is further illustrated in Fig. 5, plotting a sweep from 0.0 V to 2.0 V).
It would have been obvious to one of ordinary skill before the effective filing date to integrate Neidorff’s calibration techniques into the stress testing architecture of Jang and Zeng. A POSITA would implement the ascending voltage sweep as a “step-wise” increase from a minimum to a maximum voltage level. Neidorff teaches a parametric test method where a processor executes a voltage sweep applied in an “ascending manner.” Incorporating an ascending sweep executed by a digital processer inherently utilizes a step-wise increase originating from a starting minimum voltage level up to a maximum voltage level, demonstrated in Neidorff’s sweep from 0.0 V to 2.0 V. The motivation to structure the sweep: if a test system were to apply a massive continuous voltage or start at a maximum voltage, the electronic switches would suffer catastrophic breakdown, destroying the component and preventing the comparators from accurately capturing the exact calibrated stress limit. Therefore, it would be obvious to a POSITA to begin the sweep at a safe minimum voltage level and step-wise increase it toward a maximum limit, ensuring the test is controlled, safe and capable of pinpointing the precise calibration voltage of the switches, improving similar devices, and yield predictable results (KSR) of accurate a parametric calibration loop that safely increments test voltages to prevent component over-stress.
Regarding dependent claim 7, Jang, teaches:
The method of claim 1 ([Title], [Abstract], & [0014]-[0020])
Jang, in combination with Zeng, are silent in regard to:
wherein increasing the stress test voltage comprises step-wise increasing the stress test voltage in steps of about 100 mV.
However, Neidorff, further teaches:
wherein increasing the stress test voltage comprises step-wise increasing the stress test voltage in steps of about 100 mV (Fig. 5; [0040]-[0045], [Claim 9], [Claim 10], & [Claim 11]: teaches applying multiple voltages in an ascending sweep, that the step-wise increase (granularity) is an adjustable parameter. Defining this parameter as “about 100 mV” is an obvious design choice, supported by Fig. 5 graphical representation of a sweep utilizing 100 mV major gridline intervals, where the x-axis for the voltage sweep graph depicts Vgs (V) from 0.0 to 2.0 in exact 0.1V (100 mV) increments).
It would have been obvious to one of ordinary skill before the effective filing date to integrate Neidorff’s ascending voltage sweep, where the granularity (voltage step size) is a parameter to be determined by the user implementing the test. The combination of Jang, Zeng, and Pan establish the application of a stress test voltage. Neidorff teaches performing an ascending sweep by applying multiple voltages, illustrating the sweep in Fig. 5 using 0.1 V (100 mV) step increments along the x-axis. A POSITA implementing the combined testing method of Jang, Zeng, and Neidorff would need to select a step size for the voltage sweep, and would find it obvious to select a step size of about 100 mV (0.1V) after looking at typical semiconductor stress testing, and directly at Neidorff’s Fig. 5, which plots a sweep from 0V to 2V using 0.1V increments. The motivation to combine these teachings and optimize the sweep granularity to 100 mV is to provide a standard, logical resolution that balances test speed with accuracy to pinpoint the threshold calibration voltage without skipping critical device breakdown states. Therefore utilizing steps of about 100 mV is an obvious, routine optimization of the sweep granularity to improve similar devices, that would yield predictable results (KSR) of an accurate parametric calibration loop that safely and precisely increments test voltages.
Regarding dependent claim 14, Jang, teaches:
A method of operating the test circuit of claim 8 ([Title], [Abstract], [0014]-[0015], [0050], [0062], & [0075]-[0076]), the method comprising:
providing a threshold voltage level to the second input node of each of the comparator circuits of the set of comparator circuits (Fig. 3; [0062]-[0065]: discloses the reference voltages (VRp/VRn) act as the threshold voltage levels, routed into the current paths that feed the second inputs nodes connected to comparators 411/421);
performing a set of comparisons of each control voltage of the set of control voltages and the threshold voltage level (Fig. 4; [0062]-[0071] & [0087]-[0091]: teaches mathematical comparisons of the sensed voltages against reference thresholds);
producing a set of comparison signals, each comparison signal having a first logic value in response to the control voltage sensed at the respective control node exceeding the threshold voltage level (Fig. 4; [0062]-[0071] & [0087]-[0091]: comparators output binary logic values based on whether the threshold is exceed or not) and a second logic value in response to the control voltage sensed at the respective control node failing to exceed the threshold voltage level (Fig. 4; [0062]-[0071] & [0087]-[0091]: teaches comparators performing mathematical comparisons against reference thresholds to output logic values (0 or 1, representing logic low or high) based on whether the threshold is exceeded);
Jang, is silent in regard to:
applying a stress test voltage to the common test node;
However, Zeng, in combination with Pan, further teach:
applying a stress test voltage to the common test node (Zeng: Fig. 1B; [0017] & [0030]: teaches applying a dedicated stress voltage, applied in the combined architecture, this stress voltage is routed to the common test node GF taught by Pan; Pan: [0024], [0082], & [0084]);
It would have been obvious to one of ordinary skill before the effective filing date to utilize the dedicated stress voltage generator of Zeng to supply the stress test voltage applied to the common test node in the adapted architecture of Jang and Pan. Jang and Pan teach forcing a generalized voltage to the control nodes via a common test line GF, but lack characterizing this applied signal as a dedicated high-voltage stress test generator. Zeng teaches applying a dedicated stress voltage (Vst) from a specific stress voltage generator 32 directly to a floating gate terminal of a power transistor 12 to execute a dedicated gate stress testing mode. This substitution solves the problem of inadequately stressing power devices, providing the benefit of ensuring the applied test voltage is calibrated to exceed normal operational thresholds for proper testing. Combining these references yields the predictable result of a comprehensive testing architecture capable of safely and effectively executing a high-voltage gate stress test (KSR).
Jang, in combination with Zeng, are silent in regard to:
sensing a set of control voltages at the first input nodes of the set of comparator circuits;
in response to at least one comparison signal in the set of comparison signals having the second logic value, increasing the test voltage applied at the common test node; and
in response to each and every comparison signal in the set of comparison signals having the first logic value, interrupting both performing the set of comparisons and increasing the stress test voltage applied at the common test node, wherein a value reached by the stress test voltage applied at the common test node is determined as a calibrated stress test voltage value.
However, Jang, in combination with Pan, further teach:
sensing a set of control voltages at the first input nodes of the set of comparator circuits (Jang: [0062]-[0063]: nodes N11/N12 (and N21/N22) are the input nodes to the comparators where the voltages corresponding to the stressed/control states are sensed; Pan: [0025, [0082], & [0084]: utilizing Pan’s GL line routing, the comparator’s first input nodes physically sense the actual control voltage directly at the respective control node (gate));
It would have been obvious to one of ordinary skill before the effective filing date to apply Pan’s direct gate-sensing routing to the comparator architecture of Jang. While Jang teaches performing comparisons using a detection circuit with comparators sensing drain-side nodes, it lacks direct sensing from the gate control nodes. Pan teaches utilizing an addressable test circuit by utilizing a common force signal line GF coupled to the gate G end of each transistor under test via switches acting as coupling channels, and a dedicated sense signal line GL connected directly to the gate to act as sensing circuitry to accurately sense the actual voltage of the selected transistor’s G end. The motivation to combine these references is to solve the problem of measurement inaccuracies caused by intermediate voltage drops across source/drain regions, providing the benefit of accurate, direct gate-level stress application and sensing. This represents the use of a known technique to improve similar devices, yielding the predictable results of an accurate array of test switches receiving and sensing a control voltage directly at the control nodes (KSR).
However, Neidorff, further teaches:
in response to at least one comparison signal in the set of comparison signals having the second logic value , increasing the stress test voltage applied at the common test node (Fig. 7; [0002], [0040]-[0042], & [Claim 9]: teaches performing an ascending sweep (increasing the test voltage) while continually checking if a threshold has been met, while the threshold is not met (the comparison signal has the second/failing logic value), the voltage continues to incrementally increase); and
in response to each and every comparison signal in the set of comparison signals having the first logic value, interrupting performing the set of comparisons (Fig. 7; [0002], [0040]-[0042], & [Claim 9]: teaches interrupting (stopping) so the value can be identified, the sweeping and comparison loop the exact moment the threshold logic condition is satisfied (the first logic value is reached)) and increasing the stress test voltage applied at the common test node (Fig. 7; [0002], [0040]-[0042], & [Claim 9]: teaches interrupting (stopping) the sweeping and comparison loop the exact moment the threshold logic condition is satisfied (first logic value is reached)), wherein a value reached by the stress test voltage applied at the common test node is determined as a calibrated stress test voltage value ([0029] & [0040]-[0043]: the identified voltage value reached from the interrupted sweep is determined and designated as the threshold/calibrated limit, and this information is provided to a downstream controller/output (user circuit) to a display or external device).
It would have been obvious to one of ordinary skill before the effective filing date to incorporate the ascending voltage sweep and interrupt algorithm of Neidorff into the integrated test circuits of Jang, Zeng, and Pan. Jang, Pan, and Zeng teach applying a static stress voltage and outputting comparison logic values but lack an iterative ascending sweep algorithm designed to find a definitive calibration limit. Neidorff teaches a parametric test method where a controller iteratively increases a test voltage in an ascending sweep, interrupts the sweep when a threshold level corresponding to a specific logic state is reached, and provides the identified threshold voltage as a calibrated value on an output to test equipment. The motivation to combine these teachings is to solve the problem of applying arbitrary static stress voltages that could destroy components, thereby providing the benefit of safely and dynamically pinpointing the exact limits of the switches. This combination utilizes a known technique to improve similar devices, yielding the predictable results of an accurate parametric calibration loop that prevents catastrophic device over-stress while outputting verified calibration data (KSR).
Regarding dependent claim 16, Jang, teaches:
The test circuit of claim 15 (Fig. 2; [Title], [Abstract], [0014]-[0017], & [0049]),
Jang, in combination with Zeng, are silent in regard to:
wherein the set of comparator circuits is configured to provide the set of comparison signals to a user circuit.
However, Jang, in combination with Neidorff, further teach:
wherein the set of comparator circuits is configured to provide the set of comparison signals to a user circuit (Jang: Fig. 3; [0061]-[0065]: comparators generate the comparison signals (bits like DETp), these bits form the overall stress detection signal (DET) that is inherently provided to a downstream logical block or memory controller to register the stress degradation; Neidorff: Figs. 3A & 3B; [0029], [0037], & [0042]-[0043]: teaches an architecture where the testing controller/comparator logic provides its evaluated test signals and information via an output node 314 directly to downstream test equipment or user-facing circuit or device).
It would have been obvious to one of ordinary skill before the effective filing date to configure the comparator circuits of Jang’s adapted architecture to provide their set of comparison signals to a user circuit (such as a controller and output devices) as taught by Neidorff. Jang teaches comparator circuits generating comparison signals (DETp), but lacks the downstream routing of these signals to a dedicated external user circuit. Neidorff teaches a parametric test architecture where a controller evaluates threshold conditions and provides this diagnostic information via an output to downstream test equipment, which serves as a user circuit. The motivation to experiment and optimize by combining prior art elements/teachings according to known methods, is to solve the problem of isolated on-chip diagnostic data, enabling external systems to monitor, record, and evaluate the stress test results. This combination represents the substitution of a known output routing technique to improve similar devices, yielding the predictable result (KSR) of a test circuit that interfaces with downstream diagnostic user equipment or test circuit: to extract the internal condition of the tested components and deliver that information to the end-user or system controller for subsequent action.
Claims 8-13, 15, & 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Jang, in view of Zeng, and further in view of Pan.
Regarding independent claim 8, Jang, teaches:
A test circuit comprising (Fig. 2; [Title], [Abstract], [0015], & [0049]):
a set of electronic switches having a current path between a first node and a ground node, wherein each electronic switch comprises a respective control node (Fig. 1; [0009], [0050], & [0059]-[0062]: discloses transistors TR1-TR3 (electronic switches) with drain-source paths (current paths) between a first node (e.g., N11/N12) and ground via current sources, and each has a gate (respective control nodes), VPP acts as the first (supply) node coupled through the current path to ground);
a threshold voltage node (Fig. 3; [0016]-[0017], [0054] & [0062]: teaches nodes that provide threshold/reference voltages (VRp/VRn));
sensing circuitry ([0017] & [0062]-[0063]: the detection units contain circuitry (resistors, transistors, current sources) that senses the voltages at the control nodes and converts them into a form that can be compared by the comparators); and
a set of comparator circuits comprising comparator circuits having a first input node coupled, via the sensing circuitry, to the control node of respective electronic switches in the set of electronic switches and having second nodes coupled to the threshold voltage node (Fig. 3; [0061]: the comparators are physically coupled to the sensing circuit nodes (N11/N12), receiving voltage inputs derived from the stressed circuit and compare against the threshold/reference voltages).
a threshold voltage node (Fig. 3; [0016]-[0017], [0054], & [0062]: teaches nodes that provide threshold/reference voltages (VRp/VRn) that serve as the threshold voltage node);
Jang, in combination with Zeng, are silent in regard to:
a set of coupling channels, each coupling channel having a first end coupled to a common test node and a second end coupled to the respective control node of a respective one of the electronic switches;
a stress voltage supply source coupled to the common test node;
sensing circuitry; and
a set of comparator circuits, each comparator circuit having a first input node coupled, via the sensing circuitry, to the respective control node of the respective one of the electronic switches in the set of electronic switches and having a second input node coupled to the threshold voltage node.
However, Pan, further teaches:
a set of coupling channels, each coupling channel having a first end coupled to a common test node and a second end coupled to the respective control node of a respective one of the electronic switches (Fig. 9D; [0024], [0082], & [0084]: teaches an addressable array where a common test node GF connects via coupling channel switches SGF directly to the respective control nodes (gates) of the switches under test);
sensing circuitry (Fig. 12; [0024], [0084], & [0099]-[0100]: teaches a dedicated sense line GL and switches SGL connected directly to the gate to act as the sensing circuitry); and
It would have been obvious to one of ordinary skill before the effective filing date to apply Pan’s centralized force and sense signal lines and switching topology to the stress detection architecture of Jang as a substitution of known gate-level sensing techniques to improve similar devices. Jang teaches an array of electronic switches (transistors TR1-TR3) and comparators (411), but lacks centralized routing to and direct sensing from the gate control nodes. Pan teaches an addressable test circuit utilizing a common force signal line GF coupled to the gate G end of each transistor under test via switches SGF acting as coupling channels, and a dedicated sense signal line GL and switches SGL connected directly to the gate to act as sensing circuitry, sensing the control node voltage. The motivation to combine these references is to solve the problem of measurement inaccuracies caused by intermediate voltage drops across source/drain regions, providing the benefit of accurate, direct gate-level stress application and sensing. This represents the use of a known technique to improve similar devices, providing direct gate-level stress application and sensing. This combination yields the predictable results of an accurate array of test switches receiving and sensing a stress test voltage directly at the control nodes (KSR).
However, Zeng, in combination with Pan, further teach:
a stress voltage supply source coupled to the common test node (Zeng: Fig. 1B; [0017]: teaches a dedicated stress voltage supply source (generator 32), which is coupled to the common test node GF taught by Pan to distribute the stress voltage; Pan: [0084]);
It would have been obvious to one of ordinary skill before the effective filing date to utilize the dedicated stress voltage generator 32 of Zeng as the stress voltage supply source coupled to the common test node GF of Pan’s adapted architecture. Jang and Pan teach forcing a generalized voltage to the control nodes via a common test line GF, but lack characterizing this applied signal as a high-voltage stress test generator. Zeng teaches applying a dedicated stress voltage from a specific stress test generator 32 directly to a floating gate terminal of a power transistor 12 to execute a dedicated gate stress testing mode. This substitution solves the problem of inadequately stressing robust power devices, ensuring the applied voltage is definitively calibrated to exceed normal operational thresholds for proper testing. Combining these references, yields the predictable result of a testing architecture capable of safely and effectively executing a high-voltage gate stress test (KSR).
However, Jang, in combination with Pan, further teach:
a set of comparator circuits, each comparator circuit having a first input node coupled, via the sensing circuitry, to the respective control node of the respective one of the electronic switches in the set of electronic switches and having a second input node coupled to the threshold voltage node (Jang: Fig. 3; [0062]-[0064]: provides the set of comparators (411/421) having a second input node coupled to the threshold voltage (VRp/VRn); Pan: Fig. 12; [0025], [0082], & [0084]: provides the sensing circuitry SGL and GL that bridges the comparator’s first input node directly to the control node, “G end,” bypassing the drain-side output nodes).
It would have been obvious to one of ordinary skill before the effective filing date to apply Pan’s centralized force and sense signal lines and switching topology to the stress detection architecture of Jang. Jang teaches an array of electronic switches (TR1-TR3) and comparators 411, but lacks centralized routing to and direct sensing from the gate control nodes. Pan teaches an addressable test circuit utilizing a common force signal line GF coupled to the gate G end of each transistor under test via switches SGF acting as coupling channels, and a dedicated sense signal line GL and switches SGL connected directly to the gate to act as sensing circuitry. The motivation to combine these references is to solve the problem of measurement inaccuracies caused by intermediate voltage drops across source/drain regions, providing accurate, direct gate-level stress application and sensing. This represents the use of a known technique to improve similar devices, yielding the predictable result of an accurate array of test witches receiving and sensing a stress test voltage directly at the control nodes (KSR).
Regarding dependent claim 9, Jang, teaches:
The test circuit of claim 8 ([Title], [Abstract], [0015], & [0049]),
Jang, is silent in regard to:
wherein the respective control node of each electronic switch is configured to receive a stress test voltage
However, Jang, in combination with Zeng, further teach:
wherein the respective control node of each electronic switch is configured to receive a stress test voltage (Jang: Fig. 1; [0009]-[0011]: provides the electronic switches with control nodes (gates) configured to receive an applied voltage; Zeng: Fig. 1B; [0017] & [0030]: teaches that the voltage applied directly to the gate terminal is specifically configured as a stress test voltage (Vst) generated during a stress testing mode)
It would have been obvious to one of ordinary skill before the effective filing date to utilize the dedicated stress voltage generator 32 of Zeng to supply the stress test voltage propagated by the coupling channels to the control nodes in Pan’s adapted architecture. Jang and Pan teach forcing a generalized voltage to the control nodes via a common test line (GF), but lack characterizing this applied signal as a dedicated high-voltage stress test signal. Zeng teaches applying a dedicated stress voltage (Vst) from a specific stress voltage generator 32 directly to a floating gate terminal 118 of a power transistor 112 to execute a dedicated gate stress testing mode. The combination represents the use of a known technique to improve similar devices, solving the problem of inadequately stressing robust components by ensuring the applied test voltage exceeds normal operational thresholds. Combining these references yields the predictable results of a testing architecture capable of safely and effectively executing a gate stress test (KSR).
Jang, in combination with Zeng, are silent in regard to:
and wherein the set of coupling channels are configured to propagate application of the stress test voltage from the common test node to respective control node of each electronic switch in the set of electronic switches.
However, Pan, further teaches:
and wherein the set of coupling channels are configured to propagate application of the stress test voltage from the common test node to respective control node of each electronic switch in the set of electronic switches (Fig. 9D; [0024],[0082], & [0084]: teaches an addressable array where a common test node GF connects via coupling channels (switches SGF) directly to the control nodes (gates), these coupling channels are configured to propagate (force) the applied test voltage from the common node to the respective control nodes).
It would have been obvious to one of ordinary skill before the effective filing date to apply Pan’s centralized force signal line and switching topology to the stress detection architecture of Jang as a substitution of known routing techniques to improve similar devices. Jang teaches electronic switches with control nodes (gates of TR1-TR3) but lacks centralized routing to directly propagate a test voltage to these nodes. Pan teaches an addressable circuit utilizing a common force signal line GF coupled to the gate G end of each device under test via switches SGF acting as coupling channels to force a corresponding voltage to the gate. The motivation to combine these references is to solve the problem of limited PAD space on a semiconductor wafer, providing efficient, addressable gate-level stress application. This combination yields the predictable results of an accurate array of test switches receiving a stress test voltage directly propagated from a shared centralized source (KSR).
Regarding dependent claim 10, Jang, teaches:
The test circuit of claim 8 ([Title], [Abstract], [0015], & [0049]),
wherein the threshold voltage node is coupled to a supply voltage level at one end of a series arrangement of resistive elements referred to ground (Figs. 2-3; [0052] & [0054]: teaches generating the threshold reference voltage (Snn) using a fixed-value voltage divider circuit including a plurality of resistors inherently and structurally requires coupling a supply voltage at one end of a series arrangement of resistive elements referred to ground to tap the desired intermediate threshold voltage).
It is recognized that the citations and evidence above are derived from potentially different embodiments of a single reference. Nevertheless, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to employ combinations and sub-combinations of these complementary embodiments, to implement Jang’s alternative embodiment (a fixed voltage divider) to construct it using a series arrangement of resistive elements referred to ground, and to couple the threshold node to the control nodes of the sensing circuitry as shows in Fig. 3, where Snn feeds into the gates of T12/T21. Jang proposes replacing the dynamic block with a static voltage divider circuit made of a plurality of resistors to establish the fixed threshold/reference voltage (Snn), and while Jang does not describe the internal wiring of a standard voltage divider (i.e., tying one end to a supply voltage and the other to ground in a series arrangement), the specific arrangement is a universally understood arrangement of a voltage divider in electrical engineering. With the reference voltage (Snn) fed directly into the gates (control nodes) of the transistors (electrical switches) inside the detection signal generation circuit (sensing circuitry), that would otherwise motivate experimentation and optimization, and doing so merely combines prior art elements according to known methods to yield predictable results (KSR).
Jang, in combination with Zeng, are silent in regard to:
wherein the sensing circuitry comprises at least one resistive voltage divider referred to ground coupled to control nodes of the electronic switches in the set of electronic switches; and
However, Jang, in combination with Pan, further teach:
wherein the sensing circuitry comprises at least one resistive voltage divider referred to ground coupled to control nodes of the electronic switches in the set of electronic switches (Jang: Figs. 2-3; [0052], [0054]-[0057] & [0059]-[0065]: provides the sensing circuitry comprising a resistive voltage divider architecture (e.g., R11 and T11/T12 in a path referred to ground); Pan: Fig. 12; [0025], [0084], & [0099]-[0100]: teaches a dedicated sense line GL coupled directly to the control nodes (gates) via selectively enabled switches SGL); and
It would have been obvious to one of ordinary skill before the effective filing date to apply the direct gate-sensing routing of Pan to the resistive sensing architecture of Jang as a substitution of known techniques to improve similar devices. Jang teaches sensing circuitry using resistive elements in a current path referred to ground (resistors R11, R12 and current sources TB11, TB12 to ground), but lacks direct coupling to the actual control nodes of the tested switches. Pan teaches an addressable array where a dedicated sense line GL is selectively coupled directly to the gate (control node) via a switch SGL to sense the actual control voltage. The motivation for this substitution is to solve the problem of measurement inaccuracies caused by intermediate components, yielding the predictable result of a test circuit that directly senses actual control node voltages using accurate resistive sensing elements (KSR).
Regarding dependent claim 11, Jang, teaches:
The test circuit of claim 10 ([Title], [Abstract], [0015], & [0049]), wherein resistive elements in the at least one resistive voltage divider have resistance values based on resistance values of resistive elements in the series arrangement of resistive elements (Figs. 2-3; [0052], [0054]-[0057], & [0059]-[0065]: discloses the physical resistor elements in both the threshold series arrangement (Snn voltage divider) and the sensing resistive voltage divider (detection paths utilizing R11, R12, R21, R22). Even though it is not explicitly state that R11/R12 are sized based on the resistors in the Snn voltage divider, sizing resistors proportionately or matching them across reference and sensing circuits to cancel out system errors (i.e., thermal drift) is a well-known design parameter optimization in the art).
It is recognized that the citations and evidence above are derived from potentially different embodiments of a single reference. Nevertheless, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to employ combinations and sub-combinations of these complementary embodiments. Jang teaches generating a threshold voltage via a “voltage divider circuit including a plurality of resistors,” which constitutes the series arrangement, while simultaneously teaching resistive sensing paths, and comparing it against a sensing path that also utilizes resistors (R11, R12, R21, R22) to determine voltage drops. While Jang does not state that the specific resistance values of the sensing resistors and the reference divider are mathematically based on one another, a POSITA would inherently recognize that these values mut be proportionately sized or matched across the comparator inputs, and the resistance values of the reference divider are not based on (e.g., scaled to or matched with) resistance values of the sensing divider, any temperature variations or manufacturing process discrepancies would cause the resistance values to drift independently, leading to false stress failure detections. In analog CMOS and semiconductor circuit design, it is standard practice to construct reference voltage dividers and sensing voltage dividers using matched or proportionally scaled resistive elements. The motivation to match or scale these resistance values is to solve the problem of false comparator logic readings, canceling out thermal drift, common-mode noise, and semiconductor process variations. Applying this proportional scaling is a known technique to improve similar devices. Therefore, it would have been an obvious design choice to a POSITA to select the resistance values in the reference series arrangement based on the values in the sensing resistive divider, ensuring accuracy and stability across environmental and manufacturing variables, that would otherwise motivate experimentation and optimization, and doing so merely combines prior art elements according to known methods to yield predictable results (KSR) of an accurate test circuit that remains electrically stable under varying environmental and operational conditions.
Regarding dependent claim 12, Jang, teaches:
The test circuit of claim 8 ([Title], [Abstract], [0015], [0049]-[0050], [0062], & [0075]-[0076]), wherein the set of electronic switches (Fig. 1; [0009]: discloses the set of electronic switches (plurality of transistors TR1-TR3))
Jang, is silent in regard to:
is coupled to a set of driving circuits and wherein control nodes of electronic switches in the set of electronic switches are coupled to an output node of a respective driving circuit in the set of driving circuits, each control node configured to receive a control signal from a respective driving circuit.
However, Zeng, further teaches:
is coupled to a set of driving circuits (Fig. 2; [0018]-[0022]: discloses the blueprint for the driving circuit (VGS generator circuit 120) that is coupled switches to operate them) and wherein control nodes of electronic switches in the set of electronic switches are coupled to an output node of a respective driving circuit in the set of driving circuits (Fig. 2; [0018]-[0024]: gate (G) terminal maps to the control node of the electronic switch, the control signal line 118 exiting the VGS generator circuit maps to the output node of the respective driving circuit), each control node configured to receive a control signal from a respective driving circuit (Fig. 2; [0018]-[0024]: establishes that the control node (gate) is configured to receive the gate control signal originating from the driving circuit (VGS generator)).
It would have been obvious to one of ordinary skill before the effective filing date to apply the driving circuit architecture taught by Zeng to the array of switches taught by Jang to actively control them during normal and test modes (i.e., stress test mode). Zeng details a generator circuit (driving circuit) that has an output line coupled directly to the gate terminal (control node) of a transistor (electronic switch) to deliver a gate control signal. A POSITA would be motivated and recognize that to implement Jang’s test circuit and accurately assess the stress on the transistors, one would need to predictably drive the transistors. Therefore, it would be obvious to incorporate a set of driving circuits, as taught by Zeng’s VGS generator, coupled to the respective control nodes of the transistors in Jang’s array, where the combination of prior art reference elements would yield predictable results (KSR), of properly switching the transistors during normal operation while allowing the test framework to isolate and stress them during the test mode.
Regarding dependent claim 13, Jang, teaches:
The test circuit of claim 8 ([Title], [Abstract], [0015], [0049]-[0050], [0062], & [0075]-[0076]), wherein the electronic switches in the set of electronic switches comprise MOSFET transistors ([0005]-[0007], [0009], & [0077]).
Regarding independent claim 15, Jang, teaches:
A test circuit, comprising (Fig. 2; [Title], [Abstract], [0014]-[0017], & [0049]):
a threshold voltage node configured to receive a threshold voltage (Fig. 3; [0016]-[0017], [0054], & [0062]: teaches nodes that provide threshold/reference voltages (VRp/VRn) which serve as the threshold voltage node configured to receive the threshold voltage);
sensing circuitry ([0017] & [0062]-[0063]: the detection units contain circuitry (resistors, transistors, current sources) that senses the voltages at the control nodes and converts them into a form that can be compared by the comparators); and
wherein the set of comparator circuits is configured to perform a set of comparisons of each control voltage and the threshold voltage and to produce a set of comparison signals, each comparison signal having a first logic value in response to the control voltage sensed at the respective control node exceeding the threshold voltage (Fig. 4; [0062]-[0071] & [0087]-[0091]) and a second logic value in response to the control voltage sensed at the respective control node failing to exceed the threshold voltage (Fig. 4; [0062]-[0071] & [0087]-[0091]: teaches comparators performing mathematical comparisons against reference thresholds to output binary logic values (0 or 1, representing logic low or high) based on whether the threshold is exceeded).
Jang, is silent in regard to:
a set of electronic switches configured to have a current path between a first node and ground, wherein each electronic switch in the set of electronic switches comprises a respective control node to receive a stress test voltage,
However, Jang, in combination with Zeng, further teach:
a set of electronic switches configured to have a current path between a first node and ground, wherein each electronic switch in the set of electronic switches comprises a respective control node to receive a stress test voltage (Jang: Fig. 1; [0009], [0050], & [0059]-[0062]: discloses multiple transistors T1-T3 (electronic switches), drain-source paths (current paths) coupled through the high voltage VPP and ground, which act as the supply node, and the gates, which act as the control nodes receiving the stress voltage; Zeng: Fig. 1B; [0017] & [0030]: configures the voltage received at the gate as a dedicated stress voltage (Vst)),
It would have been obvious to one of ordinary skill before the effective filing date to utilize the dedicated stress voltage generator of Zeng to supply the stress test voltage applied to the common test node GF in the adapted architecture of Jang and Pan, resulting in the predictable variation of comprehensive testing architecture capable of safely executing gate stress tests. Jang and Pan teach forcing a generalized voltage to the control nodes via a common test line GF, but lack characterizing this applied signa source as a dedicated high-voltage stress test generator. Zeng teaches applying a dedicated stress voltage (Vst) from a specific stress voltage supply source generator 32 directly to a floating gate terminal of a power transistor 12 to execute a dedicated gate stress testing mode. The motivation for this combination is to solve the problem of inadequately stressing power devices, providing the benefit and predictable results (KSR) of ensuring the applied test voltage is generated and calibrated to exceed normal operational thresholds for proper maximum rating evaluation.
Jang, in combination with Zeng, are silent in regard to:
a set of coupling channels, each coupling channel having a first end coupled to a common test node and a second end coupled to the respective control node of a respective one of the electronic switches in the set of electronic switches, wherein the set of coupling channels are configured to propagate application of the stress test voltage from the common test node to the respective control node of each electronic switch in the set of electronic switches;
a set of comparator circuits, each comparator circuit having a first input node coupled, via the sensing circuitry, to the respective control node of the respective one of the electronic switches in the set of electronic switches and having a second input node coupled to the threshold voltage node;
wherein the sensing circuitry is configured to sense each control voltage of a set of control voltages at the node of each electronic switch in the set of electronic switches; and
However, Pan, further teaches:
a set of coupling channels, each coupling channel having a first end coupled to a common test node and a second end coupled to the respective control node of a respective one of the electronic switches in the set of electronic switches, wherein the set of coupling channels are configured to propagate application of the stress test voltage from the common test node to the respective control node of each electronic switch in the set of electronic switches (Fig. 9D; [0024], [0082], & [0084]: teaches an addressable array where a common test node GF connects via coupling channels (switches SGF) directly to the control nodes (gates/G ends), the coupling channels are configured to propagate/force the applied stress test voltage from the common node to the respective control nodes);
wherein the sensing circuitry is configured to sense each control voltage of a set of control voltages at the node of each electronic switch in the set of electronic switches ([0025], [0082], [0084], & [0099]-[0100]: Pan’s sensing circuitry (GL and SGL) is configured to sense the actual control voltages at the respective control nodes); and
It would have been obvious to one of ordinary skill before the effective filing date to apply Pan’s centralized force and sense signal lines and switching topology to the stress detection architecture of Jang as a substitution of known gate-level routing and sensing techniques to improve similar devices. Jang teaches a test circuit with electronic switches (TR1-TR3) and comparators 411, but lacks a centralized routing to and direct sensing from the gate control nodes. Pan teaches an addressable test circuit utilizing a common force signal line GF coupled to the gate G end of each transistor under test via switches SGF acting as coupling channels, and a dedicated sense signal line GL and switches SGL connected directly to the gate to act as sensing circuitry, sensing the actual gate (control node) voltage. The motivation to combine these references is to solve the problem of measurement inaccuracies caused by intermediate voltage drops across source/drain regions, providing the benefit of accurate, direct gate-level stress application and sensing. This represents the use of a known technique to improve similar devices, providing direct gate-level stress application and sensing. This combination yields the predictable results of an accurate array of test switches receiving and sensing a stress test voltage directly at the (gates) control nodes (KSR).
However, Jang, in combination with Pan, further teach:
a set of comparator circuits, each comparator circuit having a first input node coupled, via the sensing circuitry, to the respective control node of the respective one of the electronic switches in the set of electronic switches and having a second input node coupled to the threshold voltage node (Jang: Fig. 3; [0061]-[0062]: provides the comparators (411/421) having a second input node coupled to the threshold voltage (VRp/VRn) and coupled to the sensing circuit nodes (N11/N12), receiving voltage inputs derived from the stressed circuit and compare against the threshold/reference voltages; Pan: Fig. 12; [0024]-[0025], [0082], & [0084]: Pan provides sensing circuitry SGL and GL that bridges the comparator’s first input node directly to the control node G end);
It would have been obvious to one of ordinary skill before the effective filing date to apply Pan’s centralized force and sense signal lines and switching topology to the stress detection architecture of Jang as a substitution of known gate-level routing and sensing techniques to improve similar devices. Jang teaches a test circuit with electronic switches (TR1-TR3) and comparators 411, but lacks a centralized routing to and direct sensing from the gate control nodes. Pan teaches an addressable test circuit utilizing a common force signal line GF coupled to the gate G end of each transistor under test via switches SGF acting as coupling channels, and a dedicated sense signal line GL and switches SGL connected directly to the gate to act as sensing circuitry, sensing the actual gate (control node) voltage. The motivation to combine these references is to solve the problem of measurement inaccuracies caused by intermediate voltage drops across source/drain regions, providing the benefit of accurate, direct gate-level stress application and sensing. This represents the use of a known technique to improve similar devices, providing direct gate-level stress application and sensing. This combination yields the predictable results of an accurate array of test switches receiving and sensing a stress test voltage directly at the (gates) control nodes (KSR).
Jang, in combination with Zeng, are silent in regard to:
a stress voltage supply source configured to apply the stress test voltage to the common test node;
However, Zeng, in combination with Pan, further teach:
a stress voltage supply source configured to apply the stress test voltage to the common test node (Zeng: Fig. 1B; [0017] & [0030]: teaches applying a dedicated stress voltage, applied in the combined architecture, this stress voltage is routed to the common test node GF taught by Pan; Pan: [0024], [0082], & [0084]);
It would have been obvious to one of ordinary skill before the effective filing date to utilize the dedicated stress voltage generator of Zeng to supply the stress test voltage source applied to the common test node GF in the adapted architecture of Jang and Pan, resulting in the predictable variation of a comprehensive testing architecture capable of safely executing gate stress tests. Jang and Pan teach forcing a generalized voltage to the control nodes via a common test line GF, but lack characterizing this applied signal source as a dedicated high-voltage stress test generator. Zeng teaches applying a dedicated stress voltage (Vst) from a specific stress voltage generator 32 directly to a floating gate terminal of a power transistor 12 to execute a dedicated gate stress testing mode. This motivation for this combination is to solve the problem of inadequately stressing power devices, providing the benefit of ensuring the applied test voltage is generated and calibrated to exceed normal operational thresholds for proper maximum rating evaluation. Combining these references yields the predictable result of a comprehensive testing architecture capable of safely and effectively executing a high-voltage gate stress testing mode (KSR).
Regarding dependent claim 17, Jang, teaches:
The test circuit of claim 15 (Fig. 2; [Title], [Abstract], [0015]-[0017], [0049]-[0050], [0062] & [0075]-[0076]), wherein the set of electronic switches (Fig. 1; [0009]: discloses the set of electronic switches (plurality of transistors TR1-TR3)) and wherein the current path is configured to be made conductive or non-conductive based on a logic value of the control signal (Fig. 1; [0005]-[0009] & [0077]: teaches that the switches are MOSFETs and applying a logic value such as a “selectively activated” bit signal to the gate of a MOSFET makes the source-to-drain current path conductive (on) or non-conductive (off)).
Jang, is silent in regard to:
is coupled to a set of driving circuits, wherein control nodes of electronic switches in the set of electronic switches are coupled to an output node of a respective driving circuit in the set of driving circuits, each control node configured to receive a control signal from a respective driving circuit,
However, Zeng, further teaches:
is coupled to a set of driving circuits (Fig. 2; [0018]-[0022]: discloses the blueprint for the driving circuit (VGS generator circuit 120) that is coupled switches to operate them), wherein control nodes of electronic switches in the set of electronic switches are coupled to an output node of a respective driving circuit in the set of driving circuits (Fig. 2; [0018]-[0024]: gate (G) terminal maps to the control node of the electronic switch, the control signal line 118 exiting the VGS generator circuit maps to the output node of the respective driving circuit), each control node configured to receive a control signal from a respective driving circuit (Fig. 2; [0018]-[0024]: establishes that the control node (gate) is configured to receive the gate control signal originating from the driving circuit (VGS generator)),
It would have been obvious to one of ordinary skill before the effective filing date to apply the driving circuit architecture taught by Zeng to the array of switches taught by Jang to actively control them during normal and test modes (i.e., stress test mode). Zeng details a generator circuit (driving circuit) that has an output line coupled directly to the gate terminal (control node) of a transistor (electronic switch) to deliver a gate control signal. A POSITA would be motivated and recognize that to implement Jang’s array of test switches, one must drive the switches between conductive and non-conductive states during normal operation. Therefore, it would be obvious to incorporate a set of driving circuits, as taught by Zeng, coupled to the respective control nodes of the transistors in Jang’s array, where the combination of prior art reference elements would yield predictable results (KSR), of a properly functioning switch array where the current path is made conductive or non-conductive based on the logic value of the driver’s control signal.
Regarding dependent claim 18, Jang, teaches:
The test circuit of claim 15 ([Title], [Abstract], [0015]-[0017], [0050], [0062] & [0075]-[0076]), wherein electronic switches in the set of electronic switches comprise transistors (Fig. 1; [0009]).
Regarding dependent claim 19, Jang, teaches:
The test circuit of claim 18 ([Title], [Abstract] & [0015]-[0017], [0050], [0062] & [0075]-[0077]), wherein electronic switches in the set of electronic switches comprise MOSFET transistors ([0005]-[0007], [0009], & [0077]).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Jang, in view of Zeng, in view of Pan, and further in view of Grossi (US 2016/0124033 A1, Pub. Date May 5, 2016, hereinafter Grossi).
Regarding dependent claim 20, Jang, teaches:
according to claim 15 (Fig. 2; [Title], [Abstract], [0005]-[0007], [0009], [0015]-[0017], [0049]-[0050], [0062], & [0075]-[0077]),
Jang, in combination with Zeng, and Pan, are silent in regard to:
A vehicle equipped with the test circuit, wherein the vehicle comprises a battery-powered wheeled vehicle.
However, Grossi, further teaches:
A vehicle equipped with the test circuit ([0002]-[0003], [0017]-[0019] & [0024]: establishes the necessity of equipping automotive vehicles with testing circuits to diagnose electrical faults), wherein the vehicle comprises a battery-powered wheeled vehicle (Figs. 3A & 3B; [0002]-[0003] & [0034]-[0035]: teaches applying test circuits to automotive vehicles (which are universally known to be wheeled vehicles) that rely on batteries for their electrical systems).
It would have been obvious to one of ordinary skill before the effective filing date to combine the power MOSFET testing capabilities of Jang, Zeng, and Neidorff, who teach an accurate test circuit for determining the stress and health of power MOSFET electronic switches, with the automotive diagnostic teachings of Grossi. A POSITA would find it obvious to combine the teachings as vehicles become increasingly reliant on power MOSFETs for battery management and motor control, which would highly motivate a POSITA to equip a battery-powered automotive vehicle (as taught by Grossi) with specific parametric stress test circuit (as taught by Jang, Zeng, and Neidorff). The combination would allow the vehicle’s onboard diagnostics or external testing interfaces to accurately monitor the health and stress limits of its internal electronic switches, yielding predictable results (KSR) and the advantage of preventing catastrophic electrical failures in a battery-powered vehicle.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Pappas et al. (US2021/0335165A1) discloses an apparatus that comprises a backplane to attach an array of light emitting diodes (LED), the backplane comprising an array of display driver circuits, each display driver circuit of the array of display driver circuits corresponding to an LED of the array of LEDS and comprising: a current driver circuit configured to supply to a current to the corresponding LED; a control signal generator circuit configured to supply a driver control signal to the current driver circuit to control the current; and one or more monitor circuits controllable to provide access to at least one of: the current or an internal voltage of at least one of the current driver circuit or the control signal generator circuit. Tumminaro et al. (US2022/0255428A1) discloses a regulator circuit, corresponding system and method.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/HUGO NAVARRO/ Examiner, Art Unit 2858 July 21, 2026
/EMAN A ALKAFAWI/Supervisory Patent Examiner, Art Unit 2858 7/24/2026
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