Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on June 24, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 & 14-19 are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al. (US 2008/0295605 A1, Pub. Date Dec. 4, 2008, hereinafter Jang), in view of Zeng (US 2015/0381148 A1, Pub. Date Dec. 31, 2015, hereinafter Zeng), and further in view of Neidorff et al. (US 2020/0200815 A1, Pub. Date Jun. 25, 2020, hereinafter Neidorff).
Regarding independent claim 1, Jang, teaches:
A method, comprising ([Title], [Abstract] & [0015]-[0020]: provides the foundational method of stress testing):
providing a set of electronic switches having a current path between a supply node and ground, wherein each electronic switch in the set of electronic switches comprises a respective control node to receive a stress test voltage (Fig. 1; [0009], [0050] & [0059]-[0062]: provides the transistors mapping to the electronic switches, with drain-source paths (current paths) between the high voltage VPP, which acts as the supply node, and the gates, which act as the control nodes receiving the stress voltage);
based on an enable calibration signal having a first logic value, coupling a first input node of comparator circuits of a set of comparator circuits to the control node of respective electronic switches in the set of electronic switches ([0009], [0026], [0036], [0050]-[0052] & [0054]-[0066]: teaches using test mode enable signals and switching units to selectively activate/couple the sensing and detection circuitry to the function block specifically during the test mode. The test mode enables signal maps to the “enable calibration signal having a first logic value”);
providing a threshold voltage level to a second input node of comparator circuits of the set of comparator circuits (Fig. 3; [0016]-[0017], [0054] & [0062]: teaches provide threshold/reference voltages (VRp/VRn) to input nodes of comparator circuitry);
sensing at the first input nodes of the set of comparators a set of control voltages comprising control voltages sensed at the control nodes of the electronic switches in the set of electronic switches ([0062]-[0064]: first input nodes (i.e., N11/N12 and N21/N22) of the comparators sense the voltage drops corresponding to the control/stress states of the transistors);
performing a set of comparisons of the set of sensed control voltages and the threshold voltage level thereby producing a set of comparison signals having the first logic value in response to sensed control voltages in the set of sensed control voltages exceeding the threshold voltage level (Fig. 4; [0062]-[0071] & [0087]-[0091]) and a second logic value in response to the sensed control voltages in the set of sensed control voltages failing to exceed the threshold voltage level (Fig. 4; [0062]-[0071] & [0087]-[0091]: teaches comparators performing mathematical comparisons against reference thresholds to output logic values (0 or 1, representing logic low or high) based on whether the threshold is exceeded);
Jang, is silent in regard to:
coupling one end of coupling channels of a set of coupling channels to a common test node and other ends of the coupling channels of the set of coupling channels to respective control nodes of electronic switches in the set of electronic switches, wherein the set of coupling channels is configured to propagate application of a test voltage from the common test node to respective control nodes of the electronic switches in the set of electronic switches;
applying the test voltage to the common test node;
However, Zeng, further teaches:
coupling one end of coupling channels of a set of coupling channels to a common test node and other ends of the coupling channels of the set of coupling channels to respective control nodes of electronic switches in the set of electronic switches (Fig. 1B ; [0017] & [0019]-[0022]: the connection line to the gate terminal maps to the coupling channels, also discloses a common node (VarREF) coupled to a gate), wherein the set of coupling channels is configured to propagate application of a test voltage from the common test node to respective control nodes of the electronic switches in the set of electronic switches (Fig. 1B ; [0017] & [0019]-[0022]: the step of connecting the generator (common test node) to the gate terminals maps to the coupling channels to propagate the test voltage to the respective control nodes, also discloses a common node (VarREF) coupled to a gate);
applying the test voltage to the common test node (Fig. 1B; [0017]);
It would have been obvious to one of ordinary skill before the effective filing date to combine Jang’s method steps for proving the switch array (comparators), entering a test/calibration mode (using an enable signal), sensing voltages, and performing logical comparisons against a threshold and Zeng’s method of steps for coupling the stress generator to the control nodes via coupling channels to adjust the stress voltage. Jang teaches a foundational method for sensing stress in an array of electronic switches using a test mode enable signal to couple comparators to the circuit. Zeng add a crucial step of coupling a dedicated stress test voltage generator directly to the control gates of the switches under test. Zeng provides a clear mechanism for generating an adjustable test/reference voltage (VarREF). By controlling the stress enable signal (EN), additional current I2 can be switched to increase the voltage at node 124. A POSITA would be motivated to optimize a stress test by finding the maximum voltage a device can withstand before failing. The most obvious way to do this with Jang’s comparator is to: state with a low test voltage applied at the common node (e.g., by setting Zeng’s VarREF to a low value), and observe the outputs of Jang’s comparators. If any comparator indicates a failure (i.e., not all are at the first logic value), the test voltage is too high and causing stress, therefore the voltage should be decreased (or not increased further). The inverse logic as claimed: increases the voltage when at least one signal has a second logic value, which is a minor design choice (active-low vs. active-high logic) and does not change the concept. The key step is to continue increasing voltage until the point where all comparators show the pass state (the first logic, which Jang correlates with “Normal”), this voltage would occur when the calibrated stress voltage value (the maximum voltage) at which the device is still considered to be in a normal, unstressed state relative to the thresholds. Therefore, the adjustment based on comparator feedback is a standard calibration technique, and the combination of Jang’s comparator bank and Zeng’s adjustable voltage source, makes it possible and an obvious application of known circuits and methods, to yield predictable results (KSR).
Jang, in combination with Zeng, are silent in regard to:
in response to at least one comparison signal in the set of comparison signals having the second logic value, increasing the test voltage applied at the common test node;
interrupting performing the set of comparisons and increasing the test voltage applied at the common test node in response to each and every comparison signal in the set of comparison signals having the first logic value; and
providing a value reached by the test voltage applied at the common test node as a calibrated stress test voltage value to a user circuit.
However, Neidorff, further teaches:
in response to at least one comparison signal in the set of comparison signals having the second logic value, increasing the test voltage applied at the common test node (Fig. 7; [0040]-[0042]: teaches performing an ascending sweep (increasing the test voltage) while continually checking if a threshold has been met, while the threshold is not met (the comparison signal has the second/failing logic value), the voltage continues to incrementally increase);
interrupting performing the set of comparisons (Fig. 7; [0040]-[0042]: teaches that the ascending sweep finds the specific voltage value applied at the moment the threshold condition is crossed. Once the threshold is met (first logic value is reached), the sweep and comparison loop are interrupted (stopped) so the value can be identified) and increasing the test voltage applied at the common test node in response to each and every comparison signal in the set of comparison signals having the first logic value (Fig. 7; [0040]-[0042]: teaches that the ascending sweep finds the specific voltage value applied at the moment the threshold condition is crossed. This identified voltage is designated/determined as the specific threshold parameter (calibrated stress voltage value) for the device); and
providing a value reached by the test voltage applied at the common test node as a calibrated stress test voltage value to a user circuit ([0029] & [0040]-[0043]: the identified voltage from the interrupted sweep is designated as the threshold/calibrated limit, and this information is outputted by the controller (user circuit) do a display or external device).
It would have been obvious to one of ordinary skill before the effective filing date to combine Jang’s method steps for proving the switch array (comparators), entering a test/calibration mode (using an enable signal), sensing voltages, performing logical comparisons against a threshold and Zeng’s method of steps for coupling the stress generator to the control nodes via coupling channels to adjust the stress voltage, and Neidorff’s algorithmic steps of applying the test voltage, iteratively increasing it while the comparators output a fail logic state, interrupting the sweep once the passing logic state has been reaches, and providing the final calibrated value to a user circuit. Jang teaches a foundational method for sensing stress in an array of electronic switches using a test mode enable signal to couple comparators to the circuit. Zeng add a crucial step of coupling a dedicated stress test voltage generator directly to the control gates of the switches under test. A POSITA would turn to the standard Automated Test Equipment (ATE) methodologies taught by Neidorff, who teaches an algorithmic feedback loop: applying a test voltage, iteratively increasing it in an ascending sweep while checking a comparator’s logic state, and interrupting that sweep the moment the logic state flips to pinpoint the exact calibrated limit of the device. Implementing Neidorff’s iterative voltage sweep into the structural testing method taught by Jang and Zeng, would be highly predictable and an obvious design choice. The motivation to do so is to accurately calibrate the stress test voltage dynamically, thereby avoiding catastrophic over-stress while acquiring accurate parametric characterization data, by merely combining prior art elements functioning according to their established purposes, according to known methods, to yield predictable results (KSR).
Regarding dependent claim 2, Jang, teaches:
The method of claim 1, comprising ([Title], [Abstract] & [0015]-[0020])
in response to the calibration enable signal having the first logic value, coupling at least one resistive voltage divider to control nodes of the electronic switches in the set of control switches to sense the sensed control voltages via the at least one resistive voltage divider as a result ([0026], [0036],[0050]-[0052], [0054], [0058]-[0067], [0069]-[0071], [0087], [Claim 11] & [Claim 20]: test mode activation signal maps to the calibration enable signal. When activated, the test circuitry is couple. Teaches using resistors (R11, R12, etc.) to sense the voltage drops corresponding to the control/stress states. Utilizing these resistors to sense a voltage drops structurally acts as sensing via a resistive voltage divider); and
coupling a supply voltage level at one end of a series arrangement of resistive elements referred to ground thereby providing the threshold voltage level at a node intermediate the series arrangement as a result ([0049]-[0054]: teaches the method of providing the threshold voltage (Snn) using a voltage divider circuit including a plurality of resistors. Implementing a voltage divider requires coupling a supply voltage at one end of a series of resistors to ground and tapping the divided threshold voltage at an intermediate node), wherein resistive elements in the resistive voltage divider have resistance values based on resistance values of resistive elements in the series arrangement of resistive elements coupled to the supply voltage level (Figs. 2-3; [0026], [0036],[0050]-[0052], [0054]-[0067], [0069]-[0071], [0087], [Claim 11] & [Claim 20]: teaches using resistors in both the threshold generation path (voltage divider for Snn) and the sensing paths (R11/R12 and R21/R22). Even though the mathematical ratio is not stated that R11/R12 are sized based on the resistors in the Snn voltage divider sizing resistors proportionately or matching them across reference and sensing circuits to cancel out system errors (i.e., thermal drift and process variations) is a well-known design parameter optimization in the art).
It is recognized that the citations and evidence above are derived from potentially different embodiments of a single reference. Nevertheless, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to employ combinations and sub-combinations of these complementary embodiments. Jang teaches generating a reference threshold via a resistor divider and comparing it against a sensing path that also utilizes resistors (R11, R12, R21, R22) to determine voltage drops. A POSITA would recognize that if the resistance values of the reference divider are not based on (e.g., scaled to or matched with) resistance values of the sensing divider, any temperature variations or manufacturing process discrepancies would cause the resistance values to drift independently, leading to false stress failure detections. In analog CMOS and semiconductor circuit design, it is standard practice to construct reference voltage dividers and sensing voltage dividers using matched or proportionally scaled resistive elements. Therefore, it would have been an obvious design choice to a POSITA to select the resistance values in the reference series arrangement based on the values in the sensing resistive divider, ensuring accuracy and stability across environmental and manufacturing variables, that would otherwise motivate experimentation and optimization, and doing so merely combines prior art elements according to known methods to yield predictable results (KSR).
Regarding dependent claim 3, Jang, teaches:
The method of claim 1 ([Title], [Abstract] & [0015]-[0020]), wherein the set of electronic switches (Fig. 1; [0009]: discloses the set of electronic switches (plurality of transistors TR1-TR3)) wherein the current path is configured to be made at least partially conductive or non-conductive based on a logic value of the control signal (Fig. 1; [0005]-[0009] & [0077]: teaches that the switches are MOSFETs and applying a logic value such as a “selectively activated” bit signal to the gate of a MOSFET makes the source-to-drain current path conductive (on) or non-conductive (off)).
Jang, is silent in regard to:
is coupled to a set of driving circuits and wherein control nodes of electronic switches in the set of electronic switches are coupled to an output node of a respective driving circuit in the set of driving circuits, each control node configured to receive a control signal from a respective driving circuit of the set of driving circuits,
However, Zeng, further teaches:
is coupled to a set of driving circuits (Fig. 2; [0018]-[0022]: discloses the blueprint for the driving circuit (VGS generator circuit 120) that is coupled switches to operate them) and wherein control nodes of electronic switches in the set of electronic switches are coupled to an output node of a respective driving circuit in the set of driving circuits (Fig. 2; [0018]-[0024]: gate (G) terminal maps to the control node of the electronic switch, the control signal line 118 exiting the VGS generator circuit maps to the output node of the respective driving circuit), each control node configured to receive a control signal from a respective driving circuit of the set of driving circuits (Fig. 2; [0018]-[0024]: establishes that the control node (gate) is configured to receive the gate control signal originating from the driving circuit (VGS generator)),
It would have been obvious to one of ordinary skill before the effective filing date to apply the driving circuit architecture taught by Zeng to the array of transistor switches, where the switches are activated by logical bit signals, taught by Jang to actively control them during normal and test modes (i.e., stress test mode). Zeng details a VGS generator circuit (driving circuit) that has an output node coupled directly to the gate terminal (control node) of a transistor (electronic switch) to deliver a logic-based gate control signal that drives the transistor “on/off” (conductive/non-conductive). A POSITA would be motivated and recognize that to implement Jang’s array of test switches within a method of operation, one must drive the switches between conductive and non-conductive states during normal operation. Therefore, it would be obvious to incorporate a set of driving circuits, as taught by Zeng, coupled to the respective control nodes of the transistors in Jang’s array, where the combination of prior art reference elements would yield predictable results (KSR), of a properly functioning switch array where the current path is made conductive or non-conductive based on the logic value of the driver’s control signal.
Regarding dependent claim 4, Jang, teaches:
The method of claim 1 ([Title], [Abstract] & [0015]-[0020]), wherein electronic switches in the set of electronic switches comprise transistors (Fig. 1; [0009]).
Regarding dependent claim 5, Jang, teaches:
The test circuit of claim 1 ([Title], [Abstract] & [0015]-[0020]), wherein electronic switches in the set of electronic switches comprise MOSFET transistors ([0005]-[0007], [0009] & [0077]).
Regarding dependent claim 6, Jang, teaches:
The method of claim 1 ([Title], [Abstract] & [0015]-[0020]),
Jang, in combination with Zeng, are silent in regard to:
wherein increasing the test voltage comprises step-wise increasing the test voltage starting from a minimum voltage level to a maximum voltage level.
However, Neidorff, further teaches:
wherein increasing the test voltage comprises step-wise increasing the test voltage starting from a minimum voltage level to a maximum voltage level ([0040]-[0043]: teaches using a processor to apply multiple voltages in an ascending sweep, where by definition, a digital processor sweeping a voltage upwards does so in discrete increments (“step-wise”). An ascending sweep inherently dictates starting from a lower starting bound (“minimum voltage level”) and sweeping upwards until either the threshold is met or an upper safety bound (“maximum voltage level”) is reached to prevent uncontrolled destruction of the device).
It would have been obvious to one of ordinary skill before the effective filing date to integrate Neidorff’s calibration techniques into the stress testing architecture of Jang and Zeng. A POSITA would implement the ascending voltage sweep as a “step-wise” increase from a minimum to a maximum voltage level. The motivation to structure the sweep: if a test system were to apply a massive continuous voltage or start at a maximum voltage, the electronic switches would suffer catastrophic breakdown, destroying the component and preventing the comparators from accurately capturing the exact calibrated stress limit. Therefore, it would be obvious to a POSITA to begin the sweep at a safe minimum voltage level and step-wise increase it toward a maximum limit, ensuring the test is controlled, safe and capable of pinpointing the precise calibration voltage of the switches, and yield predictable results (KSR).
Regarding dependent claim 7, Jang, teaches:
The method of claim 1 ([Title], [Abstract] & [0015]-[0020])
Jang, in combination with Zeng, are silent in regard to:
wherein step-wise increasing the test voltage comprises increasing the test voltage in steps of about 100 mV.
However, Neidorff, further teaches:
wherein step-wise increasing the test voltage comprises increasing the test voltage in steps of about 100 mV (Fig. 5; [0040]-[0045]: teaches that the step-wise increase (granularity) is an adjustable parameter. Defining this parameter as “about 100 mV” is an obvious design choice, supported by Fig. 5 graphical representation of a sweep utilizing 100 mV major gridline intervals, where the x-axis for the voltage sweep graph depicts Vgs (V) from 0.0 to 2.0 in exact 0.1V (100 mV) increments).
It would have been obvious to one of ordinary skill before the effective filing date to integrate Neidorff’s ascending voltage sweep, where the granularity (voltage step size) is a parameter to be determined by the user implementing the test. A POSITA implementing the combined testing method of Jang, Zeng, and Neidorff would need to select a step size for the voltage sweep, and would find it obvious to select a step size of about 100 mV (0.1V) after looking at typical semiconductor stress testing, and directly at Neidorff’s Fig. 5, which plots a sweep from 0V to 2V using 0.1V increments. This step size provides a standard, logical resolution that balances test speed with accuracy to pinpoint the threshold calibration voltage, therefore utilizing steps of about 100 mV is an obvious, routine optimization of the sweep granularity, that would yield predictable results (KSR).
Regarding dependent claim 14, Jang, teaches:
A method of operating the test circuit of claim 8 ([Title], [Abstract], [0015], [0050], & [0062] & [0075]-[0076]), the method comprising:
providing a threshold voltage level to a second input node of comparator circuits of the set of comparator circuits (Fig. 3; [0062]-[0065]: discloses the reference voltages (VRp/VRn) act as the threshold voltage levels, routed into the current paths that feed the nodes (N12/N22) connected to comparators 411/421);
sensing a set of control voltages at the first input nodes of the set of comparators ([0062]-[0063]: nodes N11/N12 (and N21/N22) are the input nodes to the comparators where the voltages corresponding to the stressed/control states are sensed);
performing a set of comparisons of the set of sensed control voltages and a threshold voltage level thereby producing a set of comparison signals having a first logic value in response to sensed control voltages in the set of sensed control voltages exceeding the threshold voltage level (Fig. 4; [0062]-[0071] & [0087]-[0091]) and a second logic value in response to the sensed control voltages in the set of sensed control voltages failing to exceed the threshold voltage level (Fig. 4; [0062]-[0071] & [0087]-[0091]: teaches comparators performing mathematical comparisons against reference thresholds to output binary logic values (0 or 1, representing logic low or high) based on whether the threshold is exceeded);
Jang, is silent in regard to:
applying a test voltage to the test common node;
However, Zeng, further teaches:
applying a test voltage to the test common node (Fig. 1B; [0017]);
It would have been obvious to one of ordinary skill before the effective filing date to combine Jang’s comparator array to monitor the response and Zeng’s variable reference generator to adjust the stress voltage. Jang provides the monitoring and decision core, providing a complete system for monitoring a stress-related voltage (Spp) against multiple thresholds (VRp/VRn). The output is a set of comparison signals (DETp/DETn) that have specific logic values depending on whether the stress effect exceeds a threshold. Zeng provides a clear mechanism for generating an adjustable test/reference voltage (VarREF). By controlling the stress enable signal (EN), additional current I2 can be switched to increase the voltage at node 124. A POSITA would be motivated to optimize a stress test by finding the maximum voltage a device can withstand before failing. The most obvious way to do this with Jang’s comparator is to: state with a low test voltage applied at the common node (e.g., by setting Zeng’s VarREF to a low value), and observe the outputs of Jang’s comparators. If any comparator indicates a failure (i.e., not all are at the first logic value), the test voltage is too high and causing stress, therefore the voltage should be decreased (or not increased further). The inverse logic as claimed: increases the voltage when at least one signal has a second logic value, which is a minor design choice (active-low vs. active-high logic) and does not change the concept. The key step is to continue increasing voltage until the point where all comparators show the pass state (the first logic, which Jang correlates with “Normal”), this voltage would occur when the calibrated stress voltage value (the maximum voltage) at which the device is still considered to be in a normal, unstressed state relative to the thresholds. Therefore, the adjustment based on comparator feedback is a standard calibration technique, and the combination of Jang’s comparator bank and Zeng’s adjustable voltage source, makes it possible and an obvious application of known circuits and methods, to yield predictable results (KSR).
Jang, in combination with Zeng, are silent in regard to:
in response to at least one comparison signal in the set of comparison signals having the second logic value, increasing the test voltage applied at the test common node; and
increasing the test voltage applied at the common test node in response to each and every comparison signal in the set of comparison
However, Neidorff, further teaches:
in response to at least one comparison signal in the set of comparison signals having the second logic value, increasing the test voltage applied at the test common node (Fig. 7; [0040]-[0042]: teaches performing an ascending sweep (increasing the test voltage) while continually checking if a threshold has been met, while the threshold is not met (second logic value), the voltage continues to increase); and
increasing the test voltage applied at the common test node in response to each and every comparison signal in the set of comparison signals having the first logic value, wherein a value reached by the test voltage applied at the common test node is determined as a calibrated stress voltage value (Fig. 7; [0040]-[0042]: teaches that the ascending sweep finds the specific voltage value applied at the moment the threshold condition is crossed. This identified voltage is designated/determined as the specific threshold parameter (calibrated stress voltage value) for the device).
It would have been obvious to one of ordinary skill before the effective filing date to combine Jang’s comparator array /sensing architecture, Zeng’s application of a stress voltage to a gate, and Neidorff’s iterative ascending voltage sweep calibration algorithm, where Neidorff teaches applying multiple voltages in an ascending manner, comparing measured values against a threshold, and identifying the specific voltage being applied when that threshold is crossed to determine a calibration voltage limit (threshold voltage). A POSITA would find it obvious to incorporate Neidorff’s ascending voltage sweep algorithm into the testing architecture of Jang and Zeng, to apply a static stress to a circuit (Zeng) or detect a single fault state (Jang), and dynamically test and determine the exact calibrated stress/breakdown limit of the electronic switches, thereby achieving an more accurate and parametric characterization of the semiconductor’s reliability, and the combination of prior art elements according to known methods to yield predictable results.
Regarding independent claim 15, Jang, teaches:
A test circuit, comprising ([Title], [Abstract] & [0015]-[0017]):
a set of electronic switches configured to have a current path therethrough between a first node and ground (Fig. 1; [0009], [0050] & [0059]-[0062]: discloses multiple transistors (electronic switches) with drain-source paths (current paths) between a first node (e.g., N11/N12) and ground via current sources, and each has a gate (control node)),
a threshold voltage node configured to receive a threshold voltage (Fig. 3; [0016]-[0017], [0054] & [0062]: teaches nodes that provide threshold/reference voltages (VRp/VRn));
sensing circuitry ([0017] & [0062]-[0063]: the detection units contain circuitry (resistors, transistors, current sources) that senses the voltages at the control nodes and converts them into a form that can be compared by the comparators); and
a set of comparator circuits comprising comparator circuits having a first input node coupled, via the sensing circuitry, to the control node of respective electronic switches in the set of electronic switches and having second nodes coupled to the threshold voltage node (Fig. 3; [0061]: the comparators are physically coupled to the sensing circuit nodes (N11/N12), receiving voltage inputs derived from the stressed circuit and compare against the threshold/reference voltages);
wherein the sensing circuitry is configured to sense a set of control voltages at the control nodes of the electronic switches in the set of electronic switches (Fig. 3; [0061]-[0062]: detection units sense the voltage drops corresponding to the control/stress states of the transistors); and
wherein the set of comparator circuits is configured to perform a set of comparisons of the set of sensed control voltages and the threshold voltage and to produce a set of comparison signals having a first logic value in response to sensed control voltages in the set of sensed control voltages exceeding the threshold voltage (Fig. 4; [0062]-[0071] & [0087]-[0091]) and a second logic value in response to the sensed control voltages in the set of sensed control voltages failing to exceed a reference voltage (Fig. 4; [0062]-[0071] & [0087]-[0091]: teaches comparators performing mathematical comparisons against reference thresholds to output binary logic values (0 or 1, representing logic low or high) based on whether the threshold is exceeded).
Jang, is silent in regard to:
a set of coupling channels having one end coupled to a common test node and other ends coupled to respective control nodes of electronic switches in the set of electronic switches,
wherein the set of coupling channels are configured to propagate application of a test voltage from the common test node to respective control nodes of the electronic switches in the set of electronic switches;
a stress voltage supply source
However, Zeng, further teaches:
a set of coupling channels having one end coupled to a common test node and other ends coupled to respective control nodes of electronic switches in the set of electronic switches (Fig. 1B ; [0017] & [0019]-[0022]: the connection line to the gate terminal maps to the coupling channels, also discloses a common node (VarREF) coupled to a gate),
wherein the set of coupling channels are configured to propagate application of a test voltage from the common test node to respective control nodes of the electronic switches in the set of electronic switches (Fig. 1B ; [0017] & [0019]-[0022]: the physical connection routing the stress voltage from the generator (common test node) to the gate terminal maps to the coupling channel propagating the test voltage to the respective control nodes);
a stress voltage supply source ([0017]: teaches a dedicated stress voltage supply source)
It would have been obvious to one of ordinary skill before the effective filing date to combine Jang’s foundational test circuit hardware, including the set of electronic switches, the sensing circuitry, the threshold voltage nodes, and the comparator circuits configured to output first and second logic values and Zeng’s structural coupling channels and the stress voltage power supply connected directly to the control nodes (gates) of the electronic switches. To ensure the stress applied via Zeng’s pathway is accurate and effectively targets the breakdown limits of the devices without causing catastrophic failure. Therefore , it would be a predictable and obvious design choice to utilize the stress voltage generator of Zeng, and to route the calibrated stress test voltage into the detection and comparator circuitry taught by Jang, yielding predictable results (KSR).
Jang, in combination with Zeng, are silent in regard to:
wherein each electronic switch in the set of electronic switches comprises a respective control node to receive a calibrated stress test voltage;
configured to apply a calibrated stress test voltage to the common test node;
However, Neidorff, further teaches:
wherein each electronic switch in the set of electronic switches comprises a respective control node to receive a calibrated stress test voltage (Fig. 7; [0040]-[0043]: teaches identifying specific threshold voltages via sweeping to determine calibrated voltage limits, and that the voltage received at the nodes is a calibrated test voltage derived from parametric testing);
configured to apply a calibrated stress test voltage to the common test node ([0040]-[0042]: teaches calibrating the test voltage applied to a device by iteratively sweeping the voltage to find a specific threshold limit);
It would have been obvious to one of ordinary skill before the effective filing date to combine Jang’s foundational test circuit hardware, including the set of electronic switches, the sensing circuitry, the threshold voltage nodes, and the comparator circuits configured to output first and second logic values, Zeng’s structural coupling channels and the stress voltage power supply connected directly to the control nodes (gates) of the electronic switches, and Neidorff’s teachings of an iterative testing controller that identifies specific voltage limits for semiconductor devices, also providing the motivation and mechanism to apply a calibrated stress voltage rather than a static voltage. To ensure the stress applied via Zeng’s pathway is accurate and effectively targets the breakdown limits of the devices without causing catastrophic failure. A POSITA would look to standard Automated Test Equipment (ATE) parametric testing methodologies. Neidorff provides this type of methodology, teaching the calibration of a test voltage by iteratively sweeping voltages and monitoring comparator thresholds. Therefore , it would be a predictable and obvious design choice to utilize Neidorff’s calibrated testing parameters with the stress voltage generator of Zeng, and to route the calibrated stress test voltage into the detection and comparator circuitry taught by Jang, yielding predictable results (KSR) of an accurate, parametric stress testing circuit.
Regarding dependent claim 16, Jang, teaches:
The test circuit of claim 15 ([Title], [Abstract] & [0015]-[0017]), wherein the set of comparators is configured to provide the set of comparison signals (Fig. 3; [0061]-[0063]: comparators output specific comparison signals (bits like DETp), these bits form the overall stress detection signal (DET) that is inherently provided to a downstream logical block or memory controller to register the stress degradation)
Jang, in combination with Zeng, are silent in regard to:
to a user circuit.
However, Neidorff, further teaches:
to a user circuit (Figs. 3A & 3B; [0029] & [0037]: teaches routing the processed test/comparison data to a user-facing circuit or device (output 314)).
It would have been obvious to one of ordinary skill before the effective filing date to configure the comparators of Jang to provide their set comparison signals to a user circuit (such as a controller and output devices taught by Neidorff). The motivation to experiment and optimize by combining prior art elements according to known methods, is to fulfill the purpose of a diagnostic or test circuit: to extract the internal condition of the tested components and deliver that information to the end-user or system controller for subsequent action, yielding predictable results (KSR).
Regarding dependent claim 17, Jang, teaches:
The test circuit of claim 15 ([Title], [Abstract], [0015]-[0017], [0050], [0062] & [0075]-[0076]), wherein the set of electronic switches (Fig. 1; [0009]: discloses the set of electronic switches (plurality of transistors TR1-TR3)) and wherein the current path is configured to be made conductive or non-conductive based on a logic value of said control signal (Fig. 1; [0005]-[0009] & [0077]: teaches that the switches are MOSFETs and applying a logic value such as a “selectively activated” bit signal to the gate of a MOSFET makes the source-to-drain current path conductive (on) or non-conductive (off)).
Jang, is silent in regard to:
is coupled to a set of driving circuits, wherein control nodes of electronic switches in the set of electronic switches are coupled to an output node of a respective driving circuit in the set of driving circuits, each control node configured to receive a control signal from a respective driving circuit,
However, Zeng, further teaches:
is coupled to a set of driving circuits (Fig. 2; [0018]-[0022]: discloses the blueprint for the driving circuit (VGS generator circuit 120) that is coupled switches to operate them), wherein control nodes of electronic switches in the set of electronic switches are coupled to an output node of a respective driving circuit in the set of driving circuits (Fig. 2; [0018]-[0024]: gate (G) terminal maps to the control node of the electronic switch, the control signal line 118 exiting the VGS generator circuit maps to the output node of the respective driving circuit), each control node configured to receive a control signal from a respective driving circuit (Fig. 2; [0018]-[0024]: establishes that the control node (gate) is configured to receive the gate control signal originating from the driving circuit (VGS generator)),
It would have been obvious to one of ordinary skill before the effective filing date to apply the driving circuit architecture taught by Zeng to the array of switches taught by Jang to actively control them during normal and test modes (i.e., stress test mode). Zeng details a generator circuit (driving circuit) that has an output line coupled directly to the gate terminal (control node) of a transistor (electronic switch) to deliver a gate control signal. A POSITA would be motivated and recognize that to implement Jang’s array of test switches, one must drive the switches between conductive and non-conductive states during normal operation. Therefore, it would be obvious to incorporate a set of driving circuits, as taught by Zeng, coupled to the respective control nodes of the transistors in Jang’s array, where the combination of prior art reference elements would yield predictable results (KSR), of a properly functioning switch array where the current path is made conductive or non-conductive based on the logic value of the driver’s control signal.
Regarding dependent claim 18, Jang, teaches:
The test circuit of claim 15 ([Title], [Abstract], [0015]-[0017], [0050], [0062] & [0075]-[0076]), wherein electronic switches in the set of electronic switches comprise transistors (Fig. 1; [0009]).
Regarding dependent claim 19, Jang, teaches:
The test circuit of claim 18 ([Title], [Abstract] & [0015]-[0017], [0050], [0062] & [0075]-[0077]), wherein electronic switches in the set of electronic switches comprise MOSFET transistors ([0005]-[0007], [0009] & [0077]).
Claims 8-13 are rejected under 35 U.S.C. 103 as being unpatentable over Jang, in view of Zeng.
Regarding independent claim 8, Jang, teaches:
A test circuit comprising ([Title], [Abstract] & [0015]):
a set of electronic switches having a current path between a first node and a ground node, wherein each electronic switch comprises a respective control node (Fig. 1; [0009], [0050] & [0059]-[0062]: discloses multiple transistors (electronic switches) with drain-source paths (current paths) between a first node (e.g., N11/N12) and ground via current sources, and each has a gate (control node));
a threshold voltage node (Fig. 3; [0016]-[0017], [0054] & [0062]: teaches nodes that provide threshold/reference voltages (VRp/VRn));
sensing circuitry ([0017] & [0062]-[0063]: the detection units contain circuitry (resistors, transistors, current sources) that senses the voltages at the control nodes and converts them into a form that can be compared by the comparators); and
a set of comparator circuits comprising comparator circuits having a first input node coupled, via the sensing circuitry, to the control node of respective electronic switches in the set of electronic switches and having second nodes coupled to the threshold voltage node (Fig. 3; [0061]: the comparators are physically coupled to the sensing circuit nodes (N11/N12), receiving voltage inputs derived from the stressed circuit and compare against the threshold/reference voltages).
Jang, is silent in regard to:
a set of coupling channels having one end coupled to a common test node and other ends coupled to the respective control nodes of electronic switches;
a stress voltage supply source coupled to the common test node;
However, Zeng, further teaches:
a set of coupling channels having one end coupled to a common test node and other ends coupled to the respective control nodes of electronic switches (Fig. 1B ; [0017] & [0019]-[0022]: the connection line to the gate terminal maps to the coupling channels, also discloses a common node (VarREF) coupled to a gate);
a stress voltage supply source coupled to the common test node ([0017]: teaches a dedicated stress voltage supply source for testing);
It would have been obvious to one of ordinary skill before the effective filing date to combine Zeng’s direct stress voltage supply architecture with Jang’s stress detection and comparator circuitry to accurately apply and measure stress limits on semiconductor switches. A POSITA would understand the need to apply a controlled stress voltage to a common test node to evaluation the function block’s degradation. Therefore, a simple and obvious design choice for the POSITA, is to recognize that the “first voltage Spp” node in Jang is functionally equivalent to the stress node in Zeng, and that it is driven by a source (stressed function block) that provides the stress-inducing voltage. The POSITA would be motivated by experimentation and optimization to combine the teachings of Zeng with Jang to arrive at a more robust and defined stress test architecture, yielding predictable results (KSR).
Regarding dependent claim 9, Jang, teaches:
The test circuit of claim 8 ([Title], [Abstract] & [0015]), wherein each electronic switch comprises a respective control node (Fig. 1; [0009]-[0011]: discloses mapping of switches ton transistors and control nodes to gates)
Jang, is silent in regard to:
to receive a calibrated stress test voltage and wherein the set of coupling channels are configured to propagate application of a test voltage from the common test node to respective control nodes of the electronic switches in the set of electronic switches.
However, Zeng, further teaches:
to receive a calibrated stress test voltage (Fig. 1B; [0017]: maps the application of the calibrated stress test voltage to the control node) and wherein the set of coupling channels are configured to propagate application of a test voltage from the common test node to respective control nodes of the electronic switches in the set of electronic switches (Fig. 1B; [0017]-[0020]: the physical/electrical connection routing the stress voltage from the generator to the floating gate terminal maps to the “coupling channel” propagating the test voltage).
It would have been obvious to one of ordinary skill before the effective filing date to combine and modify Zeng’s stress test voltage generator to the array of transistor gates in Jang’s circuit. Jang teaches an array of switches (TR1, TR2, TR3) that undergo stress, that would require the application of elevated testing voltage. Zeng teaches this by entering a stress mode that disconnects the normal generated and connects a dedicated stress voltage generator 32 to the gate terminal (control node) to apply a stress voltage (Vst) via the coupling channel, which when applied to Jang’s plurality of transistors, the connection acts as a “set” of channels routing from the generator to the respective control nodes. It would be obvious to a POSITA to incorporate Zeng’s stress voltage generator and coupling pathways into Jang’s testing architecture to ensure the transistors receive a precise, calibrated stress test voltage, to improve the reliability and accuracy of the subsequent stress detection phase taught by Jang, and to actively and predictably stress the components before using Jang’s detection circuitry to measure the degradation stress, yielding predictable results (KSR).
Regarding dependent claim 10, Jang, teaches:
The test circuit of claim 8 ([Title], [Abstract] & [0015]), wherein the sensing circuitry comprises at least one resistive voltage divider referred to ground coupled to control nodes of the electronic switches in the set of control switches (Figs. 2-3; [0052], [0054]-[0057] & [0059]-[0065]: teaches using a voltage divider to generate the reference voltage Snn. Snn is then fed into the sensing circuitry (detection units 410a/420a) and is directly coupled to the gates (control nodes) of transistors T13 and T21, a POSITA would recognize a standard voltage divider as being “referred to ground”); and
wherein the threshold voltage node is coupled to a supply voltage level at one end of a series arrangement of resistive elements referred to ground (Figs. 2-3; [0052] & [0054]: node providing Snn acts as the threshold voltage node. A voltage divider circuit including a plurality of resistors structurally equates to a series arrangement of resistive elements spanning between a supply voltage and ground to tap off a divided threshold voltage).
It is recognized that the citations and evidence above are derived from potentially different embodiments of a single reference. Nevertheless, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to employ combinations and sub-combinations of these complementary embodiments, to implement Jang’s alternative embodiment (a fixed voltage divider) to construct it using a series arrangement of resistive elements referred to ground, and to couple the threshold node to the control nodes of the sensing circuitry as shows in Fig. 3, where Snn feeds into the gates of T12/T21. Jang proposes replacing the dynamic block with a static voltage divider circuit made of a plurality of resistors to establish the fixed threshold/reference voltage (Snn), and while Jang does not describe the internal wiring of a standard voltage divider (i.e., tying one end to a supply voltage and the other to ground in a series arrangement), the specific arrangement is a universally understood arrangement of a voltage divider in electrical engineering. With the reference voltage (Snn) fed directly into the gates (control nodes) of the transistors (electrical switches) inside the detection signal generation circuit (sensing circuitry), that would otherwise motivate experimentation and optimization, and doing so merely combines prior art elements according to known methods to yield predictable results (KSR).
Regarding dependent claim 11, Jang, teaches:
The test circuit of claim 10 ([Title], [Abstract] & [0015]), wherein resistive elements in the resistive voltage divider have resistance values based on resistance values of resistive elements in the series arrangement of resistive elements (Figs. 2-3; [0052], [0054]-[0057] & [0059]-[0065]: discloses the physical resistor elements in both the threshold series arrangement (Snn voltage divider) and the sensing resistive voltage divider (detection paths utilizing R11, R12, R21, R22). Even though it is not explicitly state that R11/R12 are sized based on the resistors in the Snn voltage divider, sizing resistors proportionately or matching them across reference and sensing circuits to cancel out system errors (i.e., thermal drift) is a well-known design parameter optimization in the art).
It is recognized that the citations and evidence above are derived from potentially different embodiments of a single reference. Nevertheless, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to employ combinations and sub-combinations of these complementary embodiments. Jang teaches generating a reference threshold via a resistor divider and comparing it against a sensing path that also utilizes resistors (R11, R12, R21, R22) to determine voltage drops. A POSITA would recognize that if the resistance values of the reference divider are not based on (e.g., scaled to or matched with) resistance values of the sensing divider, any temperature variations or manufacturing process discrepancies would cause the resistance values to drift independently, leading to false stress failure detections. In analog CMOS and semiconductor circuit design, it is standard practice to construct reference voltage dividers and sensing voltage dividers using matched or proportionally scaled resistive elements. Therefore, it would have been an obvious design choice to a POSITA to select the resistance values in the reference series arrangement based on the values in the sensing resistive divider, ensuring accuracy and stability across environmental and manufacturing variables, that would otherwise motivate experimentation and optimization, and doing so merely combines prior art elements according to known methods to yield predictable results (KSR).
Regarding dependent claim 12, Jang, teaches:
The test circuit of claim 8 ([Title], [Abstract], [0015], [0050], [0062] & [0075]-[0076]), wherein the set of electronic switches (Fig. 1; [0009]: discloses the set of electronic switches (plurality of transistors TR1-TR3))
Jang, is silent in regard to:
is coupled to a set of driving circuits and wherein control nodes of electronic switches in the set of electronic switches are coupled to an output node of a respective driving circuit in the set of driving circuits, each control node configured to receive a control signal from a respective driving circuit.
However, Zeng, further teaches:
is coupled to a set of driving circuits (Fig. 2; [0018]-[0022]: discloses the blueprint for the driving circuit (VGS generator circuit 120) that is coupled switches to operate them) and wherein control nodes of electronic switches in the set of electronic switches are coupled to an output node of a respective driving circuit in the set of driving circuits (Fig. 2; [0018]-[0024]: gate (G) terminal maps to the control node of the electronic switch, the control signal line 118 exiting the VGS generator circuit maps to the output node of the respective driving circuit), each control node configured to receive a control signal from a respective driving circuit (Fig. 2; [0018]-[0024]: establishes that the control node (gate) is configured to receive the gate control signal originating from the driving circuit (VGS generator)).
It would have been obvious to one of ordinary skill before the effective filing date to apply the driving circuit architecture taught by Zeng to the array of switches taught by Jang to actively control them during normal and test modes (i.e., stress test mode). Zeng details a generator circuit (driving circuit) that has an output line coupled directly to the gate terminal (control node) of a transistor (electronic switch) to deliver a gate control signal. A POSITA would be motivated and recognize that to implement Jang’s test circuit and accurately assess the stress on the transistors, one would need to predictably drive the transistors. Therefore, it would be obvious to incorporate a set of driving circuits, as taught by Zeng’s VGS generator, coupled to the respective control nodes of the transistors in Jang’s array, where the combination of prior art reference elements would yield predictable results (KSR), of properly switching the transistors during normal operation while allowing the test framework to isolate and stress them during the test mode.
Regarding dependent claim 13, Jang, teaches:
The test circuit of claim 8 ([Title], [Abstract], [0015], [0050], & [0062] & [0075]-[0076]), wherein the electronic switches in the set of electronic switches comprise MOSFET transistors ([0005]-[0007], [0009] & [0077]).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Jang, in view of Zeng, in view of Neidorff , and further in view of Grossi (US 2016/0124033 A1, Pub. Date May 5, 2016, hereinafter Grossi).
Regarding dependent claim 20, Jang, teaches:
according to claim 15 ([Title], [Abstract], [0005]-[0007], [0009], [0015]-[0017], [0050], [0062] & [0075]-[0077]),
Jang, in combination with Zeng, and Neidorff, are silent in regard to:
A vehicle equipped with the test circuit, wherein the vehicle comprises a battery-powered wheeled vehicle.
However, Grossi, further teaches:
A vehicle equipped with the test circuit ([0002]-[0003], [0017]-[0019] & [0024]: establishes the necessity of equipping automotive vehicles with testing circuits to diagnose electrical faults), wherein the vehicle comprises a battery-powered wheeled vehicle (Figs. 3A & 3B; [0002]-[0003] & [0034]-[0035]: teaches applying test circuits to automotive vehicles (which are universally known to be wheeled vehicles) that rely on batteries for their electrical systems).
It would have been obvious to one of ordinary skill before the effective filing date to combine the power MOSFET testing capabilities of Jang, Zeng, and Neidorff, who teach an accurate test circuit for determining the stress and health of power MOSFET electronic switches, with the automotive diagnostic teachings of Grossi. A POSITA would find it obvious to combine the teachings as vehicles become increasingly reliant on power MOSFETs for battery management and motor control, which would highly motivate a POSITA to equip a battery-powered automotive vehicle (as taught by Grossi) with specific parametric stress test circuit (as taught by Jang, Zeng, and Neidorff). The combination would allow the vehicle’s onboard diagnostics or external testing interfaces to accurately monitor the health and stress limits of its internal electronic switches, yielding predictable results (KSR) and the advantage of preventing catastrophic electrical failures in a battery-powered vehicle.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Tumminaro et al. (US2022/0255428A1) discloses a regulator circuit, corresponding system and method.
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/HUGO NAVARRO/ Examiner, Art Unit 2858 03/02/2026
/EMAN A ALKAFAWI/Supervisory Patent Examiner, Art Unit 2858 3/3/2026