Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the application No. 18/752,055 filed on June 24, 2024.
Priority
3. Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
4. Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Specification
5. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “Semiconductor Package Comprising Passive Element Structure in Cavity With Overlapped Stiffening Structure”.
Claim Rejections - 35 USC § 103
6. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
7. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
8. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
9. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
a. Determining the scope and contents of the prior art.
b. Ascertaining the differences between the prior art and the claims at issue.
c. Resolving the level of ordinary skill in the pertinent art.
d. Considering objective evidence present in the application indicating obviousness or non-obviousness.
10. Claims 1, 4, 9 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2023/0090461 A1) in view of Radhakrishnan (US 2023/0189442 A1).
Regarding independent claim 1, Kim et al. teaches a semiconductor package, comprising (Fig. 2):
a substrate (100, para [0024]);
a chip structure (120/130/120, para [0024]) on the substrate (100);
a passive element structure (105 capacitor, para [0024]) on the substrate (100) and including a passive element (105: capacitor, para [0024]); and
a stiffening structure (170/180, para [0024] called heat conductive layers) at least partially overlapping the passive element structure (105),
Kim et al. is explicitly silent of disclosing wherein, the passive element structure in the substrate; wherein a top surface of the passive element is below a top surface of the substrate.
Radhakrishnan discloses wherein (Fig. 1C upside down), the passive element structure (122, para [0021] in the recess 118, see Fig. 1A) in the substrate (110 board, para [0015]) and including a passive element (122: capacitor, para [0021]); and
wherein a top surface (upper surface) of the passive element (122) is below a top surface (111: upper/top surface) of the substrate (110).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Radhakrishnan, and modify the substrate including an cavity of Kim et al. and incorporate the capacitor inside the cavity of the substrate, in order to experience a smaller effective impedance than if mounted on the first surface 111 (para [0019]); and to enable proper operation of the board 110 (para [0021]).
Regarding claim 4, Kim et al. and Radhakrishnan teach all of the limitations of claim 1 from which this claim depends.
Kim et al. teaches wherein (Fig. 2), further comprising an adhesive layer (160) between the stiffening structure (170) and the passive element structure (105).
Regarding claim 9, Kim et al. and Radhakrishnan teach all of the limitations of claim 1 from which this claim depends.
Kim et al. teaches wherein (Fig. 2), the passive element structure (105) does not overlap the chip structure (120/130/120).
Allowable Subject Matter
11. Claims 10-20 are allowed.
12. The following is an examiner’s statement of reasons for allowance:
Claim 10: the prior art of record alone or in combination neither teaches nor makes obvious a semiconductor package, comprising:
…. the passive element structure including a passive element and a resilient insulator on the passive element;
Claim 19: the prior art of record alone or in combination neither teaches nor makes obvious a semiconductor package, comprising:
…. a passive element structure .. a resilient insulator on the passive element; .. the top surface and a lateral surface of the passive element are contact the resilient insulator,
13. Claims 2-3, 5-7, 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 2 recites …. the passive element structure includes a resilient insulator, the resilient insulator at least partially surrounding the top surface of the passive element and a lateral surface of the passive element.
Claim 5 recites …. the stiffening structure includes an upper stiffener and a lower stiffener, the upper stiffener is on the chip structure, the lower stiffener extends from the upper stiffener toward the substrate, and the lower stiffener and the chip structure are apart from each other.
Claim 8 recites …. the stiffening structure and the chip structure are apart from each other, a lateral surface of the stiffening structure is at least partially exposed, and a lateral surface of the chip structure is at least partially exposed.
14. None of the prior art of references indicated as the prior art made of record in form PTO-892, or found in the searches, disclose all the limitations of the independent claims 10, 19 (the individual limitations may be found just not in combination) that recites the passive element structure including a resilient insulator, and the resilient insulator surrounding the top surface of the passive element and a lateral surface of the passive element, and the stiffening structure and the chip structure are apart from each other. Because no reference alone, nor is there any motivation to combine the details over the prior art to create such limitations in the independent claims.
Examiner’s Note
15. Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraphs and/or columns/lines in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
16. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DIDARUL MAZUMDER whose telephone number is (571)272-8823. The examiner can normally be reached M-F 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
17. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DIDARUL A MAZUMDER/Primary Examiner, Art Unit 2812
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