Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on June 24, 2024 was in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-5 and 12-13 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lau et al. (Pub. No.: US 2023/0402441 A1).
Regarding Claim 1, Lau et al. discloses a semiconductor package, comprising: a carrier plate having a notch, a first surface and a second surface opposite to the first surface, wherein the notch extends from the first surface toward the second surface (Par. 0041-0042; Fig. 2 – carrier plate 120b (package substrate); notch 122 (groove));
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a photonic integrated circuit chip disposed within the notch (Par. 0041-0042; Fig. 2 – photonic integrated circuit chip 136b); an electronic integrated circuit chip disposed on the first surface of the carrier plate (Par. 0041-0042; Fig. 2 – electronic integrated circuit chip 134b); and an interposer substrate disposed on the first surface of the carrier plate (Par. 0006; 0018, 0027, 0036-0037, 0041-0042; Fig. 2 – this prior art clearly states “… an organic interposer may also be used to replace the film redistribution layer 140” (Par. 0027)); wherein the photonic integrated circuit chip and the electronic integrated circuit chip are disposed on two opposite surfaces of the interposer substrate respectively (Par. 0041-0042; Fig. 2).
Regarding Claim 3, Lau et al., as applied to claim 1, discloses
the semiconductor package, wherein the notch does not extend to the second surface (Fig. 2).
Regarding Claim 4, Lau et al., as applied to claim 1, discloses
the semiconductor package, wherein the photonic integrated circuit chip is entirely disposed within the notch (Fig. 2).
Regarding Claim 5, Lau et al., as applied to claim 1, discloses
the semiconductor package, wherein the photonic integrated circuit chip has a lower surface, and the lower surface of the photonic integrated circuit chip is recessed relative to the second surface (Fig. 2).
Regarding Claim 12, Lau et al. discloses a manufacturing method for a semiconductor package, comprising: providing a carrier plate, wherein the carrier plate has a notch, a first surface and a second surface opposite to the first surface, and the notch extends from the first surface toward the second surface (Par. 0041-0042; Fig. 2 – carrier plate 120b (package substrate); notch 122 (groove));; and
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disposing a photonic integrated circuit chip and an electronic integrated circuit chip on the carrier through an interposer substrate, wherein the photonic integrated circuit chip is disposed within the notch, the electronic integrated circuit chip and the interposer substrate are disposed on the first surface of the carrier plate, and the photonic integrated circuit chip and the electronic integrated circuit chip are disposed on two opposite surfaces of the interposer substrate respectively (Par. 0006; 0018, 0027, 0036-0037, 0041-0042; Fig. 2 – photonic integrated circuit chip 136b; electronic integrated circuit chip 134b; this prior art clearly states “… an organic interposer may also be used to replace the film redistribution layer 140” (Par. 0027)).
Regarding Claim 13, Lau et al., as applied to claim 12, discloses
the manufacturing method, wherein disposing the photonic integrated circuit chip and the electronic integrated circuit chip on the carrier plate comprises: disposing the electronic integrated circuit chip on the interposer substrate (Fig. 2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2, and 6-8 are rejected under 35 U.S.C. 103 as obvious over Lau et al. (Pub. No.: US 2023/0402441 A1), as applied to claim 1, further in view of Ravichandran et al. (Pub. No. : US 2024/0337799 A1).
Regarding Claim 2, Lau et al., as applied to claim 1, discloses the semiconductor package, wherein the carrier plate further has a third surface and a fourth surface opposite the third surface, the third surface and the fourth surface extend between the first surface and the second surface, and the notch further extends from the third surface toward the fourth surface (Fig. 2). Lau et al. does not explicitly disclose the semiconductor package, wherein the notch extends to the second surface from the first surface. However, Ravichandran et al., at least implicitly teaches the semiconductor package, wherein the notch extends to the second surface from the first surface (Par. 0039; Fig. 4 together with Par. 0059-0061; Fig. 9 – carrier plate (glass substrate) A; through cavities B; photonic integrated circuit chips 360 and 361 are embedded in the through cavities). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings of Ravichandran et al. to adapt the semiconductor package, wherein the notch of Lau et al. extends to the second surface from the first surface in order to accommodate photonic integrated circuit chips without increasing package height and establish electrical connection from both top and bottom of photonic integrated circuit chips if required.
Regarding Claim 6, Lau et al., as applied to claim 1, does not explicitly disclose the semiconductor package, further comprising: a passive component embedded in the interposer substrate However, Ravichandran et al., at least implicitly teaches the semiconductor package, further comprising: a passive component embedded in the interposer substrate (Par. 0003 – this prior art teaches that semiconductor package comprising passive components embedded in interposers is well known in the art). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings of Ravichandran et al. to adapt the semiconductor package, further comprising: a passive component embedded in the interposer substrate of Lau et al. in order to accommodate required functionalities without increasing the overall footprint.
Regarding Claim 7, Lau et al., as applied to claim 1, does not explicitly disclose the semiconductor package, further comprising: a package body encapsulating the electronic integrated circuit chip; wherein the electronic integrated circuit chip has an upper surface, and the upper surface is exposed from the package body. However, Ravichandran et al., at least implicitly teaches the semiconductor package, further comprising: a package body encapsulating the electronic integrated circuit chip; wherein the electronic integrated circuit chip has an upper surface, and the upper surface is exposed from the package body (Par. 0081; Fig. 15 – package body 713; electronic integrated circuit chip 711). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings of Ravichandran et al. to adapt the semiconductor package, further comprising: a package body encapsulating the electronic integrated circuit chip of Lau et al., wherein the electronic integrated circuit chip has an upper surface, and the upper surface is exposed from the package body for further processing.
Regarding Claim 8, modified Lau et al., as applied to claim 7, discloses
the semiconductor package, wherein the package body has an upper surface, and the upper surface of the package body is substantially flush with the upper surface of the electronic integrated circuit chip (Ravichandran et al. – see Fig. 15 and rejection of claim 7).
Claim 9 is rejected under 35 U.S.C. 103 as obvious over Lau et al. (Pub. No.: US 2023/0402441 A1), as applied to claim 1.
Regarding Claim 9, Lau et al., as applied to claim 1, does not explicitly disclose the semiconductor device, further comprising: a passive component disposed on the interposer substrate; and a package body encapsulating the passive component.
However, the Examiner takes OFFICIAL NOTICE that the semiconductor device, further comprising: a passive component disposed on the interposer substrate; and a package body encapsulating the passive component is well known in the art. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings well-known in the industry to adapt the semiconductor device, further comprising: a passive component disposed on the interposer substrate of Lau et al.; and a package body encapsulating the passive component in order to complete desired electrical connection and protect the passive component.
Claims 10-11, and 14-17 are rejected under 35 U.S.C. 103 as obvious over Lau et al. (Pub. No.: US 2023/0402441 A1), as applied to claim 1 and claim 12, further in view of Karhade et al. (Pub. No. : US 2025/0060531 A1).
Regarding Claim 10, Lau et al., as applied to claim 1, does not explicitly disclose the semiconductor package, further comprising: a first underfill formed between the interposer substrate and the carrier plate. However, Karhade et al., at least implicitly teaches the semiconductor package, further comprising: a first underfill formed between the interposer substrate and the carrier plate (Par. 0051; Fig. 1A – first underfill 132; interposer substrate 116; carrier plate 124). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings of Karhade et al. to adapt the semiconductor package, further comprising: a first underfill formed between the interposer substrate and the carrier plate of Lau et al., in order to protect interconnections.
Regarding Claim 11, Lau et al., as applied to claim 1, does not explicitly disclose the semiconductor package, further comprising: a second underfill formed between the interposer substrate and the photonic integrated circuit chip However, Karhade et al., at least implicitly teaches the semiconductor package, further comprising: a second underfill formed between the interposer substrate and the photonic integrated circuit chip (Par. 0051; Fig. 1A – second underfill 130; interposer substrate 116; photonic integrated circuit chip 102). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings of Karhade et al. to adapt the semiconductor package, further comprising: a second underfill formed between the interposer substrate and the photonic integrated circuit chip of Lau et al., in order to protect interconnections.
Regarding Claim 14, Lau et al., as applied to claim 13, does not explicitly disclose the semiconductor package, wherein disposing the photonic integrated circuit chip and the electronic integrated circuit chip on the carrier plate comprises: forming a package body to encapsulate the electronic integrated circuit chip to form a multi-chip heterogeneous integrated module; and disposing the multi-chip heterogeneous integrated module on the carrier plate. However, Karhade et al., at least implicitly teaches the semiconductor package, wherein disposing the photonic integrated circuit chip and the electronic integrated circuit chip on the carrier plate comprises: forming a package body to encapsulate the electronic integrated circuit chip to form a multi-chip heterogeneous integrated module; and disposing the multi-chip heterogeneous integrated module on the carrier plate (Par. 0052; Fig. 1A – package body 136; electronic integrated circuit chip 118; carrier plate 124). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings of Karhade et al. the semiconductor package, wherein disposing the photonic integrated circuit chip and the electronic integrated circuit chip on the carrier plate comprises: forming a package body to encapsulate the electronic integrated circuit chip of Lau et al., to form a multi-chip heterogeneous integrated module; and disposing the multi-chip heterogeneous integrated module on the carrier plate in order to protect associated components from the outside environment and give them mechanical stability.
Regarding Claim 15, Lau et al., as applied to claim 14, discloses
the manufacturing method, wherein forming the package body to encapsulate the electronic integrated circuit chip comprises: planarizing the package body until an upper surface of the package body is substantially flush with an upper surface of the electronic integrated circuit chip (Fig. 1A).
Regarding Claim 16, Lau et al., as applied to claim 12, does not explicitly disclose the manufacturing method, wherein disposing the photonic integrated circuit chip and the electronic integrated circuit chip on the carrier plate comprises: forming a first underfill between the interposer substrate and the carrier plate. However, Karhade et al., at least implicitly teaches the manufacturing method, wherein disposing the photonic integrated circuit chip and the electronic integrated circuit chip on the carrier plate comprises: forming a first underfill between the interposer substrate and the carrier plate (Par. 0051; Fig. 1A – underfill 132; interposer substrate 116; carrier plate 124). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings of Karhade et al. to adapt the manufacturing method, wherein disposing the photonic integrated circuit chip and the electronic integrated circuit chip on the carrier plate comprises: forming a first underfill between the interposer substrate and the carrier plate of Lau et al., in order to protect interconnections.
Regarding Claim 17, Lau et al., as applied to claim 12, does not explicitly disclose the manufacturing method, wherein disposing the PIC and the electronic integrated circuit chip on the carrier plate comprises: forming a second underfill between the interposer substrate and the photonic integrated circuit chip. However, Karhade et al., at least implicitly teaches the manufacturing method, wherein disposing the PIC and the electronic integrated circuit chip on the carrier plate comprises: forming a second underfill between the interposer substrate and the photonic integrated circuit chip (Par. 0051; Fig. 1A – second underfill 130; interposer substrate 116; photonic integrated circuit chip 102). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings of Karhade et al. to adapt the manufacturing method, wherein disposing the PIC and the electronic integrated circuit chip on the carrier plate comprises: forming a second underfill between the interposer substrate and the photonic integrated circuit chip of Lau et al., in order to protect interconnections.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kang et al. (Pub. No.: US 2025/0105231 A1)– This prior art teaches a semiconductor package, comprising: a carrier plate (100) having a notch (100_R), a first surface and a second surface opposite to the first surface, wherein the notch extends from the first surface toward the second surface; a photonic integrated circuit chip (200) disposed within the notch; an electronic integrated circuit chip (500) disposed on the first surface of the carrier plate; and an interposer substrate (300) disposed on the first surface of the carrier plate; wherein the photonic integrated circuit chip (200) and the electronic integrated circuit chip (500) are disposed on two opposite surfaces of the interposer substrate (300) respectively (Fig. 3).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SYED I GHEYAS whose telephone number is (571)272-0592. The examiner can normally be reached on Monday-Friday from 8:30 AM - 5:30 PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley, can be reached at telephone number (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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09/03/2026
/SYED I GHEYAS/Primary Examiner, Art Unit 2893
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