Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-10 and 13-15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Son et al. (US PGPub 2021/0082941).
Claim 1: Son teaches (Fig. 3) a microelectronic device, comprising: a stack structure (ST) comprising tiers vertically stacked relative to one another and respectively including conductive material (EL) and insulative material (ILD) vertically neighboring the conductive material, the stack structure further comprising: a memory array region (CAR) including vertically extending strings (VS) of memory cells therein; and a contact region (CNR) horizontally offset from the memory array region and including a staircase structure (STS) having steps comprising edges of the tiers; a lateral contact structure (SL) vertically underlying the stack structure and within a horizontal area of the memory array region, the lateral contact structure coupled to the vertically extending strings of memory cells; and an etch-resistant structure (ILD2) vertically underlying the stack structure and within a horizontal area of the contact region, the etch-resistant structure at a vertical position of the lateral contact structure and having a different material composition than the lateral contact structure. The claim language does not state that the lateral contact is entirely within the horizontal area of the memory array.
Claim 2: Son teaches (Fig. 3) the lateral contact structure is substantially confined within the horizontal area of the memory array region of the stack structure; and the etch-resistant structure is substantially confined outside of the horizontal area of the memory array region of the stack structure. The claim language does not state that the lateral contact is entirely confined within the horizontal area of the memory array or that the etch-resistant structure is entirely confined outside of the memory array.
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Claim 3: Son teaches (Fig. 3) the stack structure further comprises an intervening region (boxed area) horizontally interposed between the memory array region and the contact region thereof, a horizontal area of the intervening region substantially free of any of the vertically extending strings of memory cells and of any portions the staircase structure.
Claim 4: Son teaches (Fig. 3) one or more of the lateral contact structure and the etch-resistant structure horizontally extend into the horizontal area of the intervening region.
Claim 5: Son teaches (Fig. 3) the lateral contact structure is substantially confined within the horizontal area of the memory array region of the stack structure; and the etch-resistant structure is substantially confined within a combination of the horizontal area of the contact region and the horizontal area of the intervening region of the stack structure.
Claim 6. The microelectronic device of claim 5, further comprising additional contact structures within the horizontal area of the intervening region of the stack structure, the additional contact structures respectively vertically extending through each of portions of the stack structure and the etch-resistant structure with the horizontal area of the intervening region of the stack structure.
Claim 7: Son teaches (Fig. 3) [0030-0041] the lateral contact structure comprises additional conductive material; and the etch-resistant structure comprises one or more of insulative material, semiconductor material, and further conductive material having a different material composition than the additional conductive material.
Claim 8: Son teaches (Fig. 3) [0030-0041] the etch-resistant structure comprises one or more of dielectric oxide material and dielectric nitride material.
Claim 9: Son teaches [0067] the etch-resistant structure (ILD2,ESL) comprises doped semiconductor material. It also doesn’t disqualify a multi-layer structure for the etch-resistant structure.
Claim 10: Son teaches (Fig. 3) (see claim 1) a memory device, comprising: a stack structure comprising a vertically alternating sequence of insulative material and conductive material arranged in tiers, the stack structure including: a memory array region; and a staircase region neighboring the memory array region and including a staircase structure including steps comprising horizontal ends of at least some of the tiers; a conductive, lateral contact structure underlying the stack structure at a first vertical position and substantially confined within a horizontal area of the memory array region; cell pillar structures within the horizontal area of the memory array region, the cell pillar structures respectively comprising semiconductor material vertically extending through the stack structure and coupled to the conductive, lateral contact structure; and an additional structure (PIL) underlying the stack structure at the first vertical position and substantially confined outside of the horizontal area of the memory array region.
Claim 13: Son teaches (Fig. 3) [0030-0041] material compositions of the conductive material of the tiers of the stack structure and of the conductive, lateral contact structure are different than one another.
Claim 14: Son teaches (Fig. 3) [0030-0041] material compositions of the conductive material of the tiers of the stack structure and of the conductive, lateral contact structure substantially the same as one another.
Claim 15: Son teaches (Fig. 3) vertical contact structures (PLG) vertically extending through the stack structure and respectively in physical contact with the additional structure.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Son et al. (US PGPub 2021/0082941) in view of Lim et al. (US PGPub 2016/0163732)
Claim 16: Son teaches (Fig. 3) a 3D NAND Flash memory device, comprising: a stack structure comprising blocks horizontally extending in parallel in a first direction and separated from one another in a second direction orthogonal to the first direction, the blocks respectively comprising tiers individually including conductive material vertically neighboring insulative material; strings of memory cells within horizontal areas of and vertically extending through the blocks of the stack structure; lateral contact structures vertically underlying the stack structure and respectively coupled to a group of the strings of memory cells. Son doesn’t teach additional structures within the horizontal areas of and vertically underlying the blocks of the stack structure, the additional structures at a vertical elevation of the lateral contact structures and respectively horizontally offset in the first direction from all of the strings of memory cells. Lim teaches additional structures (18) within the horizontal areas of and vertically underlying the blocks of the stack structure, the additional structures at a vertical elevation of the lateral contact structures (14) and respectively horizontally offset in the first direction from all of the strings of memory cells to allow for bitline connections to the peripheral circuit. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the device taught by Son to have had additional structures within the horizontal areas of and vertically underlying the blocks of the stack structure, the additional structures at a vertical elevation of the lateral contact structures and respectively horizontally offset in the first direction from all of the strings of memory cells to allow for bitline connections through the stack to connect to underlying peripheral circuits as taught by Lim (Fig. 3A)
Claim 17: Lim teaches (Fig. 6) the blocks respectively include one or more staircase structures horizontally offset in the first direction from the strings of memory cells, the one or more staircase structures individually including steps comprising horizontal ends of at least some of the tiers; and the additional structures (16’) horizontally overlap the one or more staircase structures of the blocks in each of the first direction and the second direction.
Claim 18: Lim teaches (Fig. 6) vertical dimensions of responsive ones of the lateral contact structures and of respective ones of the additional structures are substantially equal to one another; and horizontal dimensions in the second direction of the respective one of the lateral contact structures and of the respective ones of the additional structures are substantially equal to one another.
Claim 19: Son teaches (Fig. 3) responsive ones of the lateral contact structures physically contact respective ones of the additional structures.
Claim 20: Son teaches (Fig. 3) control logic circuitry vertically underlying the lateral contact structures and the additional structures and in electrical communication with the strings of memory cells.
Claim(s) 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Son et al. (US PGPub 2021/0082941), as applied to claim 10 above, and further in view of Lim et al. (US PGPub 2016/0163732)
Regarding claim 11, as described above, Son substantially reads on the invention as claimed, except Son does not teach the heights of the additional structure and the conductive, lateral contact structure are substantially equal to one another. Lim teaches the heights of the additional structure and the conductive, lateral contact structure are substantially equal to one another so that a bit line connection can pass through the lateral contact structure to peripheral devices. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the structures taught by Son to have the same height as the additional structure only has to make room for the bitline to pass through the lateral contact structure as taught by Lim (Fig. 3A).
Claim 12: Lim teaches the material compositions of the additional structure [0085] and the conductive, lateral contact structure [0080] are different than one another.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SARAH KATE SALERNO whose telephone number is (571)270-1266. The examiner can normally be reached M-F 6:30am-2:30pm.
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/SARAH K SALERNO/Primary Examiner, Art Unit 2814
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