The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al. (U.S. Patent Application Publication 2023/0298631, hereinafter referred to as Park).
As to claim 1, Park teaches 11. A chip package comprising: a substrate; an integrated circuit (IC) interposer die mounted on the substrate; a compute die stack mounted on the IC interposer die; and a memory stack mounted on the substrate and electrically coupled to the compute die stack through the IC interposer die. [Fig. 1; ¶0040]
As to claim 2, Park teaches 2. The chip package of claim 1, wherein the compute die stack further comprises: at least a first compute die and a second compute die. [120 Fig. 1; ¶0047]
As to claim 3, Park teaches 3. The chip package of claim 2, wherein the first compute die and the second compute die comprises central processing unit (CPU) cores. [Fig. 1; ¶0037]
As to claim 4, Park teaches 4. The chip package of claim 2, wherein the first compute die comprises accelerated compute cores and the second compute die comprises central processing unit (CPU) cores. [Fig. 1; ¶0037]
As to claim 5, Park teaches 5. The chip package of claim 2, wherein the first compute die and the second compute die comprises accelerated compute cores. [Fig. 1; ¶0037]
As to claim 6, Park teaches 6. The chip package of claim 1, wherein the compute die stack further comprises: mold compound disposed between the memory stack and the compute die stack; and a metal layer formed in contact with a top surface of the mold compound, a top surface of the memory stack, and a top surface of the compute die stack. [Fig. 1; ¶0003~0004]
As to claim 7, Park teaches 7. The chip package of claim 6 further comprising: a lid disposed over the memory stack and the compute die stack; and thermal interface material disposed in contact with both the metal layer and the lid. [Fig. 1; ¶0003~0004]
As to claim 8, Park teaches 8. The chip package of claim 1, wherein: the substrate is an interposer; and the interposer is mounted on a package substrate. [Fig. 1; ¶0003~0004]
As to claim 9, Park teaches 9. The chip package of claim 2, wherein the first compute die is hybrid bonded to one or both of the second compute die and the IC interposer die. [Fig. 1; ¶0040]
As to claim 10, Park teaches 10. The chip package of claim 2, wherein the IC interposer die further comprises: memory controller circuity coupled to both the first and second compute dies without routing signals through the package substrate; and cache memory circuity coupled to both the first and second compute dies without routing signals through the substrate. [Fig. 1; ¶0003~0004]
As to claim 11, Park teaches 11. The chip package of claim 2, wherein the IC interposer die further comprises: a network on a chip (NOC) circuitry; peripheral component interconnect express (PCIe) circuity; memory physical layer (PHY) circuitry configured to communicate with the memory stack; die to die PHY configured to communicate with at least one of the first and second compute dies; and I/O PHY configured to communicate with a device remote from the chip package. [Fig. 1; ¶0040]
As to claim 12, Park teaches 12. A chip package comprising: a substrate; a first integrated circuit (IC) interposer die mounted on the substrate, the first IC interposer die comprising memory controller circuity; a first compute die stack mounted on the first IC interposer die, the first compute die stack comprising at least a first compute die and a second compute die both communicatively coupled with the memory controller circuity; a first memory stack mounted on the substrate and electrically coupled to the memory controller circuity through the substrate; a lid disposed over the first memory stack and the first compute die stack; and thermal interface material disposed in contact with both the first compute die stack and the lid. [Fig. 1; ¶0003~0004; 0040]
As to claim 13, Park teaches 13. The chip package of claim 12 further comprising: a second compute die stack mounted on the first IC interposer die, the second compute die stack comprising a plurality of compute dies communicatively coupled with the memory controller circuity. [Fig. 1; ¶0003~0004; 0040]
As to claim 14, Park teaches 14. The chip package of claim 12 further comprising: a second memory stack mounted on the substrate and electrically coupled to the memory controller circuity through the substrate. [Fig. 1; ¶0003~0004; 0040]
As to claim 15, Park teaches 15. The chip package of claim 12 further comprising: a second IC interposer die mounted on the substrate, the second IC interposer die comprising memory controller circuity; a second compute die stack mounted on the second IC interposer die, the second compute die stack comprising a plurality of compute dies communicatively coupled with the memory controller circuity of the second IC interposer die; and a second memory stack mounted on the substrate and electrically coupled to the memory controller circuity of the second IC interposer die through the substrate. [Fig. 1; ¶0003~0004; 0040]
As to claim 16, Park teaches 16. The chip package of claim 12, wherein at least one or both of the first compute die and the second compute die comprises central processing unit (CPU) cores. [Fig. 1; ¶0003~0004; 0037]
As to claim 17, Park teaches 17. The chip package of claim 12, wherein at least one or both of the first compute die and the second compute die comprises accelerated compute cores. [Fig. 1; ¶0037]
As to claim 18, Park teaches 18. The chip package of claim 12, wherein the first compute die stack further comprises: a carrier die disposed over first and second compute dies; and a circuit free dummy die disposed between the first IC interposer die and the carrier die, wherein the dummy die is fusion bonded to at least two of the first compute die, the second compute die, the first IC interposer die, and the carrier die. [Fig. 1; ¶0003~0004; 0040]
As to claim 19, Park teaches 19. The chip package of claim 12, wherein the first IC interposer die further comprises: cache memory circuity coupled to both the first and second compute dies without routing signals through the substrate, a network on a chip (NOC) circuitry; peripheral component interconnect express (PCIe) circuity; memory physical layer (PHY) circuitry configured to communicate with the first memory stack; die to die PHY configured to communicate with at least one of the first and second compute dies; and I/O PHY configured to communicate with a device remote from the chip package. [Fig. 1; ¶0003~0004; 0040]
As to claim 20, Park teaches 20. A method for fabricating a chip package, the method comprising: mounting a compute die stack on an integrated circuit (IC) interposer die, the compute die stack comprising at least two compute IC dies; mounting the IC interposer die on a substrate; and mounting a memory stack on the substrate, the memory stack electrically coupled to the compute die stack through the IC interposer die. [Fig. 1; ¶0003~0004; 0040]
Conclusion
Claims 1-20 are rejected as explained above.
The prior art made of record in the PTO-892 form and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAEHWAN OH whose telephone number is (571) 270-5800. The examiner can normally be reached on Monday - Friday 9:00 AM-5:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached on 408-918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAEHWAN OH/
Primary Examiner, Art Unit 2899
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