DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5, 7, 13-14 and 16-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2024/0079454 A1 to Wirths et al. (hereinafter “Wirths”).
Regarding claim 1, Wirths discloses a semiconductor device, comprising a plurality of units, wherein each of the units comprises:
a substrate (SiC power device having plurality of transistor cells 50 having substrate layer 20A; Figs. 3A-3D; paragraphs [0057]-[0058]);
a drift layer, located on a first surface of the substrate (substrate layer 20B on layer 20A may act as a drift layer; Figs. 3A-3D; paragraphs [0057]-[0058]);
a fin, located on a first surface of the drift layer (stack 30 disposed on first surface of layer 20B; Fig. 3A);
a first doped region, located in the fin and extending from a top surface of the fin toward the drift layer (n-type source layer 36 located in stack 30 and extending from top surface of stack 30 toward layer 20B; Fig 3A; paragraph [0059]);
a second doped region, located in the substrate and extending from a second surface of the substrate toward the first surface of the substrate (layer 20A comprises n+ doped region within first cell 50 extending from first and second surfaces thereof; Fig. 3A; paragraph [0058]);
a first doped pillar, located in the drift layer and extending from the first surface of the drift layer toward a second surface of the drift layer (layer 20B comprises n- doped region within first cell 50 extending between first and second surfaces thereof; Fig. 3A; paragraph [0058]); and
a first gate structure, between the first doped region and the first doped pillar, on a first side wall of the fin, and extending to the first surface of the drift layer (gate electrode layer 45 and insulating layers 42-44, 80 form gate structure disposed partially between layer 36 and n- doped region of layer 20B, where gate structure is disposed along first side wall of stack 30 and extends to first surface of layer 20B; Fig. 3A; paragraphs [0061], [0066]).
Regarding claim 2, Wirths discloses the semiconductor device according to claim 1, further comprising: a second doped pillar, located in the drift layer and extending from the first surface of the drift layer toward the second surface of the drift layer (layer 20B comprises n- doped region within second cell 50 extending between first and second surfaces thereof; Fig. 3A; paragraph [0058]); and a second gate structure, between the first doped region and the second doped pillar, on a second side wall of the fin, and extending to the first surface of the drift layer (second gate structure within first cell 50 disposed between layer 36 and n- doped region of layer 20B of second cell 50, where second gate structure is disposed along second side wall of stack 30 and extends to first surface of layer 20B; Fig. 3A; paragraphs [0061], [0066]).
Regarding claim 3, Wirths discloses the semiconductor device according to claim 2, wherein cross sections of the first gate structure and the second gate structure are respectively L-shaped (first and second gate structures within first cell 50 have an L-shaped cross-section; Fig. 3A).
Regarding claim 5, Wirths discloses the semiconductor device according to claim 2, wherein the first doped region and the second doped region have a first conductivity type (n+ doped region of layer 20A and layer 36; paragraphs [0058]-[0059]), and the first doped pillar and the second doped pillar have a second conductivity type (n- doped regions of layer 20B; paragraph [0058]).
Regarding claim 7, Wirths discloses the semiconductor device according to claim 5, further comprising: a first conductor layer, electrically connected to the first doped regions, the first doped pillars, and the second doped pillars of the units; and a second conductor layer, electrically connected to the second doped regions of the units (first and second main electrodes 52, 54 electrically connected to stack 30 and layers 20A, 20B of each cell 50; Fig. 3A; paragraphs [0061], [0066]).
Regarding claim 13, Wirths discloses a method of fabricating a semiconductor device, comprising:
providing a substrate (SiC power device having plurality of transistor cells 50 having substrate layer 20A; Figs. 3A-3D; paragraphs [0057]-[0058]);
forming a plurality of units, wherein forming each of the units comprises: forming a drift layer on a first surface of the substrate (substrate layer 20B on layer 20A may act as a drift layer; Figs. 3A-3D; paragraphs [0057]-[0058]);
forming a first doped region in the drift layer (n-type source layer 36 located in stack 30 and extending from top surface of stack 30 toward layer 20B; Fig 3A; paragraph [0059]);
patterning a part of the drift layer with the first doped region to form a fin (stack 30 disposed on first surface of layer 20B; Fig. 3A);
forming a second doped region on a second surface of the substrate (layer 20A comprises n+ doped region within first cell 50 extending from first and second surfaces thereof; Fig. 3A; paragraph [0058]);
forming a first doped pillar extending from a first surface of the drift layer toward a second surface of the drift layer in the drift layer (layer 20B comprises n- doped region within first cell 50 extending between first and second surfaces thereof; Fig. 3A; paragraph [0058]); and
forming a first gate structure extending to the first surface of the drift layer between the first doped region and the first doped pillar and on a first side wall of the fin (gate electrode layer 45 and insulating layers 42-44, 80 form gate structure disposed partially between layer 36 and n- doped region of layer 20B, where gate structure is disposed along first side wall of stack 30 and extends to first surface of layer 20B; Fig. 3A; paragraphs [0061], [0066]).
Regarding claim 14, Wirths discloses the method of fabricating the semiconductor device according to claim 13, further comprising: forming a second doped pillar extending from the first surface of the drift layer toward the second surface of the drift layer in the drift layer (layer 20B comprises n- doped region within second cell 50 extending between first and second surfaces thereof; Fig. 3A; paragraph [0058]); and forming a second gate structure extending to the first surface of the drift layer between the first doped region and the second doped pillar and on a second side wall of the fin (second gate structure within first cell 50 disposed between layer 36 and n- doped region of layer 20B of second cell 50, where second gate structure is disposed along second side wall of stack 30 and extends to first surface of layer 20B; Fig. 3A; paragraphs [0061], [0066]).
Regarding claim 16, Wirths discloses the method of fabricating the semiconductor device according to claim 14, wherein the first doped region and the second doped region have a first conductivity type (n+ doped region of layer 20A and layer 36; paragraphs [0058]-[0059]), and the first doped pillar and the second doped pillar have a second conductivity type (n- doped regions of layer 20B; paragraph [0058]).
Regarding claim 17, Wirths discloses the method of fabricating the semiconductor device according to claim 16, further comprising: forming a first conductor layer electrically connected to the first doped regions, the first doped pillars, and the second doped pillars of the units; and forming a second conductor layer electrically connected to the second doped regions of the units (first and second main electrodes 52, 54 electrically connected to stack 30 and layers 20A, 20B of each cell 50; Fig. 3A; paragraphs [0061], [0066]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being obvious over Wirths in view of US 2022/0384634 A1 to Baringhaus et al. (hereinafter “Baringhaus”).
Regarding claim 4, Wirths discloses the semiconductor device according to claim 2. Wirths fails to disclose further comprising: a first isolation structure, located in the drift layer and spaced from the first doped pillar by a non-zero distance in a lateral direction; and a second isolation structure, located in the drift layer and spaced from the second doped pillar by a non-zero distance in the lateral direction.
However, Baringhaus discloses a first isolation structure, located in the drift layer and spaced from the first doped pillar by a non-zero distance in a lateral direction; and a second isolation structure, located in the drift layer and spaced from the second doped pillar by a non-zero distance in the lateral direction (isolation structures having cavities disposed within drift region 206 and spaced apart in lateral direction from doped regions 208, 210; Fig. 14; paragraph [0037]).
Wirths and Baringhaus are both considered to be analogous to the claimed invention because they are in the same field of power field effect transistors. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Wirths to incorporate the teaching of Baringhaus in order to potentially provide improved breakdown voltage and associated higher voltage handling capability, reduced surface electric fields, and better control of depletion and impact ionization.
Claim 6 is rejected under 35 U.S.C. 103 as being obvious over Wirths in view of US 2021/0013314 A1 to Hu et al. (hereinafter “Hu”).
Regarding claim 6, Wirths discloses the semiconductor device according to claim 5. Wirths fails to disclose the first doped region comprises Si or Sn dopants; and the first doped pillar and the second doped pillar comprise NiO, Cu2O, In203, ZnO, IGZO, other oxide semiconductors, or p-type GaN.
However, Hu discloses the first doped region comprises Si or Sn dopants; and the first doped pillar and the second doped pillar comprise NiO, Cu2O, In203, ZnO, IGZO, other oxide semiconductors, or p-type GaN (Ga2O3 drift layer 2 having pillar-shaped channel 3 extending therefrom which may be doped with Si; paragraphs [0038]-[0039]).
Wirths and Hu are both considered to be analogous to the claimed invention because they are in the same field of power field effect transistors. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Wirths to incorporate the teaching of Hu in order to potentially provide improved control of n-type carrier density with shallow donors, use of well-known and widely available dopants for Ga2O3, and higher current density and overall power density or efficiency in high-voltage switching applications.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Wirths.
Regarding claim 12, Wirths discloses the semiconductor device according to claim 1, wherein the substrate comprises an n-type heavily doped Ga2O3 substrate or an n-type heavily doped SiC substrate, and a material of the drift layer comprises n-type lightly doped Ga2O3 or n-type lightly doped SiC (layer 20A comprises heavily doped n+ SiC layer and layer 20B comprises lightly doped n- SiC layer; paragraph [0058]).
Wirths fails to explicitly disclose the substrate comprises an n-type heavily doped Ga2O3 substrate or an n-type heavily doped GaN substrate, and a material of the drift layer comprises n-type lightly doped Ga2O3 or n-type lightly doped GaN.
However, Wirths already discloses the layer 20A comprising heavily doped n+ SiC and the layer 20B comprising lightly doped n- SiC.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Wirths to utilize GaN instead of SiC in order to potentially provide lower specific on-resistance, higher power density, and faster switching capability. Further, paragraph [0017] of Baringhaus discloses that SiC and GaN are each common materials interchangeably selected for substrate and drift layers in the field of power FETs.
Allowable Subject Matter
Claims 8-11, 15 and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 2013/0146885 A1 to Brown et al. and US 2024/0055495 A1 to Wirths et al. each discloses power FETs having related multilayered structures and relative structural orientations.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IAN DEGRASSE whose telephone number is (571) 272-0261. The examiner can normally be reached Monday through Friday 8:30a until 5:00p.
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/IAN DEGRASSE/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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